Mobile phone chipmaker Qualcomm Technologies Inc. (San Diego, Calif.) is undertaking an evaluation of a sequential 3D circuit integration process that is linked to the FD-SOI process, developed by French research institute CEA-Leti (Grenoble, France).
Sequential 3D integration is a next-generation process that goes beyond the use of through-silicon-vias (TSVs) to attach separate die to each other or to enable the use of silicon interposers. With sequential 3D technology 2D layers of circuits are processed followed by bonding with a silicon-on-insulator layer in which another 2D circuit layer is created together with connections down to the first layer. This process can be continued to create further layers.
Comparison of TSV-based on sequential 3D integration. Source: Leti.
To create the next active layer inter-layer dielectric (ILD) is deposited and planarized followed by molecular boning of SOI substrate to the ILD at 200 degrees C.
Unlike 3D-TSV technologies sequential 3D integration processes all the functions in a single semiconductor manufacturing flow. Inter-layer registration accuracy is much higher with sequential 3D integration as standard lithography processe are used to align layers and it allows the connection of active areas between layers at the transistor level.
Leti claims that users of sequential 3D integration can achieve a 50 percent gain in area and a 30 percent gain in performance compared with the same circuit in a single 2D layer. This is roughly equivalent to the traditional improvement achieved by moving to a subsequent process node but the sequential 3D technology is expected to be less complex and expensive to implement, making this technology a potential alternative to conventional planar scaling solutions.
For example by staying at 28nm minimum geometries IC designers could avoid the complexity of multiple patterning and extreme ultra-violet lithography. Qualcomm Technologies is now set to provide a critical assessment of the technology in the context of practical applications and its potential for industrialization.
At least part of Leti’s experience with sequential 3D integration has been built up in the context of fully-depleted silicon-on-insulator (FDSOI) manufacturing processes. The introduction of the interlayer dielectric and bonding of a fresh wafer to the first to produce a new active silicon area offers synergies with FDSOI processes. Leti has demonstrated the process down to the 50nm minimum geometry as of October 2012.
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