Semiconductor Value Chain

Renesas Warms to FDSOI

07 October 2013

Japan's Renesas Electronics Corp. has contributed to a research paper on fully depleted silicon-on-insulator (FDSOI) chip manufacturing technology and expects to be part of a movement to bring the technology to market.

Other companies such as IC design foundry Verisilicon Holdings Co. Ltd. and Chinese foundry Semiconductor Manufacturing International Corp. (SMIC) could also be interested in using the technology.

The ultra-thin body and buried oxide (UTBB) FDSOI is an alternative manufacturing process to bulk CMOS and to the follow-on manufacturing process based on FinFETs that stand up from the silicon surface. While the low power and high performance characteristics of FDSOI are promising, manufacturing leaders such as Intel and TSMC have committed themselves to the FinFET technology having expressed doubts about the cost of the engineered wafers that are the FDSOI starting point.

A Renesas employees is named as an author on a paper scheduled to be presented at the upcoming International Electron Devices Meeting, due to be held Dec. 7 to 9 in Washington, D.C. The paper includes an extensive author list with engineers from STMicroelectronics, Soitec, Leti, IBM, Globalfoundries and Renesas. The paper is expected to detail UTBB FDSOI devices with a 20-nm gate length for the 14-nm node. This is the next generation of the technology, which has already been developed at the 28-nm node.

So far, FDSOI has been pioneered by ST, which has a pilot production capacity at its fab in Crolles, near Grenoble, France. However, this would not be enough to satisfy high volume applications and Globalfoundries has agreed to provide that capability from its fab in Dresden, Germany.

When asked if inclusion of Renesas on the author list meant the company intended to use the FDSOI process commercially, a spokesperson said: "This is actually a contributed paper written by several companies including Renesas and Globalfoundries regarding research of the FDSOI semiconductor manufacturing process. So there is no solid plan at the moment but we expect to cooperate with other companies to make this happen."

Speaking at the International Electronics Forum held in Dublin last week, Wayne Dai, chairman and CEO of custom silicon solutions vendor VeriSilicon, said his company is working on developing IP support for FDSOI and that an FDSOI conference is soon to take place in Shanghai, where others, such as SMIC, may attend.

Speaking at the same event Jack Harding, president and CEO of IP, design and manufacturing services company eSilicon Corp., said: "I do see this [FDSOI] ecosystem building up. We're being paid to do it. When you see EDA companies moving spontaneously to adopt it, then you know it is going to be a success. Until then it is being provided to the very large fabless chip companies that are self-contained. They don't need extensive IP support."

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