Memory and Storage

Micron to Spotlight ReRAM at ISSCC

07 November 2013

SK Hynix and Micron Technology will report NAND flash non-volatile memories at 16-nm critical dimensions at the 2014 International Solid-State Circuits Conference (ISSCC) in San Francisco in February. But the more eagerly awaited papers are likely to be from Samsung on 3-D NAND and from Micron on a 16-Gbit (Gb) resistive RAM memory.

It is also notable that there are no papers on phase-change memory (PCM) or magnetoresistive RAM (MRAM) scheduled to appear in Session 19 on non-volatile memory.

The 16-nm node represents the leading edge in NAND flash memory production, but it could be the last node that will be produced before NAND flash goes vertical.

Samsung is due to report on a 128-Gb, 3-bit multi-level cell vertical NAND flash memory with 24 stacked layers. It seems likely that this is a similar device to that which Samsung announced was in volume production in August. The chip accomplishes 50 megabyte (MB) per second write throughput with 3,000 cycles endurance for typical embedded applications. An extended endurance of 35,000 cycles endurance can be achieved at a lower write throughput of 33 MB per second for data center and enterprise SSD applications.

However, the relatively low endurance cycling may indicate that this paper discusses a scaled version of the commercial chip that is closer to 10-nm class geometry. One of the expected benefits of moving to a vertical NAND structure is that it should allow a relaxation of geometry and a return to nodes at around 45 nm or 40 nm. Further details may be revealed in the ISSCC advanced program.

Meanwhile, Micron (Boise, Idaho) is scheduled to report on a 16-Gb ReRAM with a 200-MB-per-second write bandwidth and 1-gigabyte (GB) per second read bandwidth through a DDR interface implemented in a 27-nm manufacturing process. No details have been provided yet on the material regime Micron is using for its ReRAM.

In the first paper of session 19, Micron reports on a 128-Gb MLC NAND flash memory using a 16-nm planar cell with high-k dielectric/metal gate cell architecture.

Micron announced it was sampling a 16-nm, 128-Gb MLC NAND in July, with plans to be in full production by the fourth quarter. What Micron is reporting may be different than that device. In paper 19.2, SK Hynix describes a 64-Gb MLC NAND flash memory also implemented in 16-nm process. It supports 400 Mb per second through a NV-DDR2 interface for high-speed data transaction.

In paper 19.4, authors from National TsingHua University (Hsinchu, Taiwan) are due to present an embedded 1-Mb ReRAM in 28-nm process with 0.27-to-1V read. It is not clear what material system is in use.

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