Heterogeneous integration, advanced packaging and AI/HPC workloads are forcing more test insertions and heavier system-level testing (SLT) leading to longer, more numerous test steps in the semiconductor manufacturing cycle.
Not surprisingly, this means a heavier investment/cost burden on fabs as more testing equipment/processes are needed.
Prior to the advancement of chiplets, advanced packaging and miniaturization, test costs were typically about 2% of the total cost of the chip. However, this cost has been rising and will be an even larger part of overall chip production costs in the future.
To bring these costs back to normalcy, SLT may be key.
What is SLT?
SLT is an emerging methodology in semiconductor manufacturing where a chip, packaged device or multi-die assembly is tested in as close to real-world system operational conditions as possible.
Unlike automated test equipment (ATE) testing, SLT runs the test as part of a full system environment that uses firmware, software, I/O traffic, memory subsystems and thermal conditions. The advantage here is that the semiconductors are “exposed” to defects in the system that earlier stages of testing may have missed.
SLT is emerging due to the complexity of semiconductor manufacturing particularly with mixed integration, chiplet integration, HPC and AI accelerators becoming commonplace. In the future, SLT could be common test insertion to the overall production flow at fabs.
Reducing costs, defects
According to Teradyne, it is becoming imperative to optimize the design-manufacture-test loop to continue to reduce defect escape rates. This will also help reduce the cost of tests to continue to realize yield targets and quality levels of semiconductors. This means re-thinking test flows and system-level testing (SLT), Teradyne said.
As chips become more complex, test processes will follow. This includes known good die (KGD) testing, final test and SLT growing in importance. How do vendors keep costs down while achieving desired results? Teradyne said the following ways will help:
- Using common tools between designers and test engineers to collaborate for chip verification and fault debugging.
- Moving some tests earlier to reduce defects before KGD integration.
- Reducing costs by deferring some tests to later in the process.
- Applying analytics to adjust the test process before and during high volume manufacturing.
In October 2025, Teradyne launched its Titan HP SLT platform designed for AI and cloud infrastructure markets.
The testing tool is designed to push the boundaries of power consumption and thermal output to test these AI and cloud infrastructure semiconductors in real-world conditions, Teradyne said. The current model supports up to 2 kilowatts of power, but the company plans to support 4 KW in the future.
SLT expansion
Teradyne is not the only one expanding its presence in the anticipated demand for SLT. Japanese automatic test equipment vendor Advantest agreed that SLT is a growing element of its product strategy.
A crucial part of this strategy will be to link all test insertions from design to wafer sort, final test and SLT. This type of coordinated test insertion will be required for higher test volumes and new methods like SLT will be a major part of this future, Advantest said.
Advantest said it has “made strategic and complementary investments” in adjacent testing areas that has “not only strengthened our existing core markets but also expanded our business into system-level testing, test interfaces, sockets and data infrastructure.”
Major cost driver
Trade organization SEMI named SLT as one of the major future cost drivers for capital equipment and fabs as part of an augment to traditional ATE testing. Other future costs include:
- Increased test time for additional scan and functional testing
- Increased testing at the wafer to produce KGD
- Increased cost of handling equipment
- Increased use of device calibration/trimming at test
SEMI said the increased use of chiplets in advanced packaging to realize optimized end-system products is one of the primary driving forces behind the emergence of SLT.
SEMI added that SLT should not be viewed as a traditional last-stage test insertion, but as system-oriented testing that needs to occur at every stage from wafer sort, through die stack, packaging, assembled sub-systems and finally deployed end-system. This may include periodic testing either offline or in-line due to aging-related degradation of electronic components.
Even if full-fledged SLT is not feasible, some aspects of the end-system will need to be considered as individual components are tested. As a result, SLT content development methodology will likely adopt the use of digital twins to enable system modeling, co-optimization and verification, SEMI said.
SLT can be more cost effective in the production process as semiconductors become more complex. Source: Teradyne
Balancing ATE and SLT
Advantest said that moving forward, total cost of quality will be critical for the future of semiconductor testing.
This means balancing the needs of both ATE and SLT across the entire design process.
SLT was traditionally viewed as a complement to ATE but it is moving to part of an overall testing strategy where both testing types are used in operations.
While traditional ATE is not going away, Teradyne said that SLT can be beneficial to costs as device complexity continues. At some point, it is cheaper to implement SLT than to continue with ATE.
Teradyne said SLT is “very cost-effective at screening out the last few, difficult to find faults at the end of the test flow” and “adding SLT to the end of the existing ATE test flow is often the most cost-effective strategy” for applications with high requirements.
Ultimately, combining ATE and SLT is a solution for maintaining high-quality testing levels but with lower costs, the company said.
