Electronic Design Automation

Cadence expands deal with Samsung on 3D-IC design

21 October 2022

Cadence Design Systems Inc. has expanded its collaboration with Samsung Foundry to accelerate the use of 3D-IC design.

As part of the deal, the reference flow featuring Cadence Integrity 3D-IC platform will help to create next generation hyperscale computing, mobile, automotive and artificial intelligence (AI) applications.

The power, performance and area (PPA) of the 3D-IC can be impacted when chips are stacked in a 3D-iC configuration instead of in a 2D configuration due to the presence of large 3D structures such as TSVs, which connect the stacked chips.

Cadence’s Integrity 3D-IC platform lets users create multiple TSV insertion scenarios and device an optimal 3D structure placement on a die with reduced wirelength penalties while boosting PPA and productivity, Cadence said.

Additionally, the platform allows users to design, plan, implement and sign off from a single cockpit.

“Customers creating stacked die designs at advanced nodes are always looking to make use of the benefits of our technologies without compromising PPA,” said SangYun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics. “The enablement that resulted from our collaboration with Cadence leverages advanced 3D-IC capabilities that provide our mutual customers with innovative techniques to build 3D designs without giving up PPA due to the additional structures introduced with multi-die stacking.”

To contact the author of this article, email engineering360editors@globalspec.com

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