Electronic Design Automation

Cadence expands embedded processing IP core family

06 July 2022
The Tensilica ConnX 110 and ConnX 120 DSP cores offer flexiblility for lidar, radr and communications in automotive, consumer and industrial markets. Source: Cadence

Cadence Design Systems Inc. has expanded its Tensilica ConnX family with two new digital signal processing (DSP) intellectual property (IP) cores designed for lidar and radar embedded processing in the automotive, consumer and industrial sectors.

The ConnX 110 and ConnX 120 DSPs share a common instruction set architecture (ISA) for design flexibility and combined with the other two DSP cores in Cadence’s portfolio, cover a range from low to the ultra-high-end systems.

The 128-bit ConnX 110 DPSP and 256-bit ConnX 120 DSP feature an N-way programming model, are compatible with the other two DSP cores in Cadence’s portfolio, support Cadence’s Tensilica Instruction Extension language that allows users to tailor the instruction set, add special data types and integrated interfaces between the DSP and external logic.

Additional features include:

  • Optimized instruction set for radar, lidar and communication applications.
  • Common instruction set and programming model for code to be written once and utilized across different SIMD widths.
  • Single instruction/multiple data (SIMD) performance for complex math operations based on 8-, 16- and 32-bit fixed point and half-, standard- and double-precision floating point.
  • Optimized for small memory footprint and low-power signal processing.
  • Optional acceleration operations for linear-feedback shift, convolutional encoding, single peak search and dual peak search.
  • Offers Viterbi and Turbo decoders.
To contact the author of this article, email PBrown@globalspec.com


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