Semiconductor Equipment

Strategies for wafer testing continue to improve

15 December 2021
The T5221 has the capacity for wafer-level testing on up to 1,152 devices at once. Source: Advantest Corp.

An essential aspect of the semiconductor fabrication process is wafer testing, and over time a variety of strategies for improving its efficiency, maximizing its cost-effectiveness and accelerating time-to-market has emerged.

Multiprobe testing

One example is the multiprobe design, which tests multiple dies in parallel. The market is growing, according to automated test and measurement equipment manufacturer Advantest; the company recently reported worldwide sales of NAND wafer test equipment for multi-stacked probers at approximately $100 million per year in U.S. dollars, accounting for an estimated 7% of the total memory market. The company has responded to that trend with a new high-throughput memory tester for NAND flash devices designed to perform functional testing of chips while delivering highly accurate timing, repeatability and failure detection.

The T5221 system features a controller built with a combined-array architecture. This allows it to manage up to 12 test stations simultaneously, each with independent testing capabilities, and creates the capacity for performing wafer-level testing on up to 1,152 devices at once. While ideal for mass production, the system can also be docked with single- or dual-wafer probers for use in engineering environments.

Advantest also noted in a press release that the T5221 offers significant improvements over the company’s previous design, which incorporated a nonvolatile memory tester and a standalone prober. The T5221 test stations are housed within the multi-wafer prober itself, greatly reducing floor space. Data-transfer speeds are also more than five times faster.

Parametric testing

The P002A is a flexible and configurable parametric test system. Source: Keysight TechnologiesThe P002A is a flexible and configurable parametric test system. Source: Keysight TechnologiesAnother strategy is parametric testing, which derives from statistical principles — the testing process can be accelerated by allowing assumptions, based on a probability distribution, to be made about unknown parameters. Advanced design and validation solutions provider Keysight Technologies has taken this approach with a new parallel parametric test system, the P9002A.

According to the company, the system offers a flexible option structure for up to 100 channels of parallel test resources, including test capabilities required for parametric tests at each test resource. Software compatibility with the Keysight SPECS semiconductor parametric test shell, plus system compatibility and data correlation with the Keysight 4080 series parametric tester, enables customers to utilize existing tester programs, test plans and probe cards. The company also offers a licensing structure that allows options to be added based upon test requirements.

In a press release, Keysight underscored the importance of improving testing approaches as a response to the global semiconductor shortage, which has created a growing demand in a variety of areas including digital devices, home appliances and the automotive industry. Test parameters are also increasing as the industry strives to adapt new materials, incorporate miniaturization and 3D packaging processes, and design for commercial applications in areas like 5G and artificial intelligence.

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To contact the author of this article, email engineering360editors@globalspec.com


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