Memory and Storage

PCI Express 5.0 switches introduced by Microchip

03 February 2021

Microchip Technology Inc. has introduced what it claims is the world’s first PCI Express (PCIe) 5.0 switch that doubles the interconnect performance for compute, high speed networking and NVM Express storage.

The switch family supports 28 lanes to 100 lanes and up to 48 non-transparent bridges (NTBs). Source: MicrochipThe switch family supports 28 lanes to 100 lanes and up to 48 non-transparent bridges (NTBs). Source: MicrochipThe Switchtec PFX PCIe 5.0 family can be combined with Microchip’s XpressConnect retimers to deliver a portfolio of PCIe Gen 5 infrastructure solutions with interoperability. The switch family supports 28 lanes to 100 lanes and up to 48 non-transparent bridges (NTBs). Other capabilities include hot-and-surprise-plug as well as secure boot authentication and provides a suite of debug and diagnostic features such as internal PCIe analyzers supporting transaction layer packet (TLP) generation and analysis and on-chip non-obtrusive SerDes eye capture capabilities.

Rapid system bring-up and debug is also supported with ChipLink, a graphical user interface based device configuration and topology viewer that provides full access to the PFX PCIe switch’s register, counters, diagnostics and forensic capture capabilities.

“Intel’s upcoming Sapphire Rapids Xeon processors will implement PCI Express 5.0 and Compute Express Link running up to 32.0 GT/s to deliver the low-latency and high-bandwidth I/O solutions our customers need to deploy,” said Debendra Das Sharma, director of I/O technology and standards and fellow at Intel.

To contact the author of this article, email GlobalSpecEditors@globalspec.com


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