Microchip Technology Inc. has introduced its first compute express link (CXL) smart memory controllers to give more flexibility to data centers.
The introduction of the smart memory controllers comes just a few days after SK Hynix introduced its first CXL DDR5 DRAM form factor.
CXL enables microprocessors, graphic processors and system-on-chips to use CXL interfaces to connect either DDR4 or DDR5 memory. The solution delivers more memory bandwidth per core, more memory capacity per core and lowers the cost of ownership in the data center. Additionally, the form factor allows data centers to upgrade or switch memory options while traditional memory configurations are fixed.
Called the SMC 2000, the memory controllers are designed to the CXL 1.1 and CXL 2.0 specifications, DDR4 and DDR5 JEDEC standards and support PCIe 5.0 specification speeds. The SMC 2000 16x32G is a high-capacity controller with 16 lanes operating at 32 GT/s and supports two channels of DDR4-3200 or DDR5-4800. This results in a reduction in the required number of host CPU or SoC pins per memory channel.
CXL memory modules provide an effective mechanism to increase the memory bandwidth available to processing cores. Data center operators can deploy a broader range of ratios for memory to CPU cores depending on needs that results in improved memory utilization and lower cost of ownership, Microchip said.
Microchip called the CXL platform one of the biggest industry disruptions in recent years and will bring a new serial interface to CPUS to expand memory beyond parallel DDR interface for improving the performance and longevity of data centers.
