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Semiconductors and Components

Leti and Mapper Develop Individualized Chips with Maskless Lithography in CMOS Process

05 March 2018

300 mm Si wafer exposed on FLX-1200 multi-beam tool at 5 kV on N40 BEOL stack. Source: Leti300 mm Si wafer exposed on FLX-1200 multi-beam tool at 5 kV on N40 BEOL stack. Source: Leti

Leti, a research institute of CEA Tech, and Mapper Lithography, a provider of maskless lithography equipment for the semiconductor and nanofabrication industries, have announced a low-cost cyber-security breakthrough that encrypts individual chips with a code.

The non-falsifiable code is generated by using a unique chip design that leverages direct multi-beam writing in a process that fits in a conventional CMOS flow with an extra level of lithography and without photomasks. Throughput on Mapper's FLX-1200 tool installed at Leti is compatible with optical systems.

The markets for these chips include data security, traceability and combatting imports of counterfeit chips.

Leti, a specialist in electron-beam lithography, and Mapper, a Dutch company, presented a paper on the breakthrough, "Process development of a maskless N40 via level for security application with multi-beam lithography," at SPIE Advanced Lithography 2018 in San Jose, Calif. The paper demonstrates a patterning integration that is compliant with standard CMOS 40 nm process flow.

The maskless lithography system, based on massively parallel electron-beam writing capability developed by Mapper, is designed for high-volume specialty chips and low-volume advanced logic.

Leti and Mapper are demonstrating the breakthrough for their customers at Leti's facility in Grenoble, France.

To contact the author of this article, email [email protected]


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