The current optical lithography is expected to give way, at least with the most advanced layers of semiconductor devices, to extreme-ultraviolet (EUV) lithography, multiple-beam electron-beam lithography and direct-write e-beam lithography. Directed self-assembly and nanoimprint lithography are also anticipated to find useful applications in patterning chips.
EUV Demo Tool Copyright: ASMLThe standard binary photomask is expected to stay the same size, at six inches by six inches by 0.25 inch, for the next-generation of lithography. Other than that, the proliferation of masks needed for 193i immersion lithography is expected to be alleviated by the introduction of EUV lithography into high-volume manufacturing (HVM), requiring fewer masks and exposures.
Still, the shrinking of integrated-circuit dimensions to seven nanometers (nm) and five nm will present a new host of challenges, making it harder to find the inevitable defects in masks, which can produce defects in chips. Actinic photomask inspection is touted as the solution to the issue, yet funding of that technology is currently a sore point for chipmakers and their suppliers of semiconductor equipment.
ASML Holding reported the imminent shipment of its newest EUV lithography scanner, the fourth-generation NXE:3350B, with plans for two more shipments in the fourth quarter. The NXE:3350B system has an overlay of 1.0 nanometer—a 50% improvement from its NXE:3300B predecessor—according to the company.
The eBeam Initiative, an industry organization, last month reported increasing optimism for high-volume manufacturing implementation of EUV lithography in its annual survey of “industry luminaries.” The 64 respondents picked EUV as the most likely method of next-generation lithography to be used in at least one manufacturing step by 2020, with an average confidence rating of 62%.
The organization also surveyed captive and merchant mask manufacturers for the first time, and the survey found that 96% of them expect multi-beam technology to be used for high-volume manufacturing mask writing by the end of 2018, compared with 65% of semiconductor equipment suppliers.
The survey was unveiled at the annual SPIE Photomask Technology Conference in Monterey, California. The conference heard from a number of 
SPIE Photomask Technology Conference in Monterey, California.industry executives and researchers, reporting on the progress or lack of progress in mask technology, particularly in EUV masks and pellicles, mask data preparation, mask inspection, and metrology, among other topics.
“With EUV lithography, significant mask-making infrastructure needs to be brought to maturity,” Harry Levinson of GlobalFoundries says in his keynote presentation at the opening of the conference, and following speakers over three days offered more details on that statement.
Ted Liang, principal engineer in the Intel Mask Operations (IMO), noted that Intel has been working on EUV masks for more than a decade. “For masks, there has been steady progress,” he says. “Blank quality continues to improve. Large defects are mostly eliminated.”
Pattern inspection, pellicle integration and through-pellicle inspection are three areas that are important to high-volume manufacturing with EUV scanners, Liang concludes.
Yalin Xiong of KLA-Tencor, speaking during a panel session entitled “EUV Mask Readiness: Do We Finally Kick the Ball?” (a reference to the Peanuts comic strip, where Lucy always yanks away the football before Charlie Brown can kick it), questioned whether the industry should fund development of actinic photomask inspection or allow equipment vendors to shoulder those costs on their own.
While most of the conference witnessed dispassionate discourse, the panel session saw a candid and mildly contentious discussion about “economy” and “investment” in next-generation technologies.
“Long-term solutions that require investment are risky,” Xiong says. “They require a new collaboration model.”
He adds, “Photomask is an enabling technology for lithography. We have to make our voice heard. The voice [of the mask community] is not heard in lithography. We need to be louder.”
Takahiro Onoue of HOYA wrapped up the panel session with a presentation on EUV mask blanks. His final bullet points asserted that future production of defect-free, high-grade EUV mask blanks requires “support from stakeholders for investment toward HVM.”
ASML EUV scanner Copyright: ASMLIntel, Samsung Electronics and Taiwan Semiconductor Manufacturing have all made equity investments in ASML to aid the development of EUV systems, and Intel is widely believed to have placed an order with ASML this year for 15 EUV scanners to signal its confidence in EUV technology. Jeff Farnsworth of Intel Mask Operations said during the SPIE conference’s panel discussion, “We’re serious about implementing EUV on 7 nanometer.”
Of course, only time will tell if EUV succeeds, after years of delays and setbacks, principally in development of sufficient power for the laser light sources required. The semiconductor industry seems to be hedging its bets on next-generation lithography technology, while continuing to rely on its workhorse immersion lithography equipment to turn out 10-nm chips and beyond.
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