The obvious way to accomplish this has been to increase the size of the FPGA die and associated package, which leads to higher costs and a bigger "footprint" occupying valuable PC board real estate; alternatively, designers can build some sort of multiplexing front end. Yet many of these added ports are relatively low speed interfaces, and so really don't need a direct connection to the FPGA.
The FPC401 quad port controller from Texas Instruments is designed to address this issue, as seen in Figure 1. This IC aggregates all low-speed control and I2C signals across four ports into a single, user-selectable I2C or SPI bus to the host FPGA. Designers can combine multiple front port controllers to manage up to 56 ports with a single two-wire interface. It also includes advanced LED features for port-status indication, such as programmable blinking and dimming.
Fig. 1 The FPC401 Port Controller Aggregator from Texas Instruments addresses the problem of providing an increasing number of I/O ports for FPGA, while minimizing circuit complexity along with PC-board routing and footprint.(Source: Texas Instruments)
Unlike some simpler aggregation approaches which require polling through every address, which is time-consuming and inefficient if many addresses have no changes, the FPC401 supports direct addressing to every port and so eliminates the need for polling. It also eliminates the need for discrete I2C multiplexers, LED drivers, and high-pin-count processor-control devices, which simplifies the BOM.
Clocking rate for the I2C interface is up to 1 MHz, and up to 10 MHz for the SPI interface. The controller supports a broadcast mode, which implements a "write" to all ports simultaneously across all FPC401s; this is useful for system resets and restarts.
By using this controller function to aggregate I/O for the FPGA, the PC-board layout and routing congestion is reduced, while layout is simplified. The required pin count of the FPGA package is also shrunk, which broadens the possible FPGAs which designers can consider. To further save space and maintain signal integrity, the FPC401's 56-lead QFN package (just 5 mm × 11mm) can be placed on the bottom side of the PCB underneath the press-fit connector; this also simplifies routing and leaves more top-side PC board space available. The IC uses a separate host-side I/O voltage of 1.8 V to 3.3 V for maximum flexibility in supply-rail match-up.
Texas Instruments offers an evaluation board for the FPC401, as seen in Figure 2. The FPC401EVM aggregates all low-speed signals of two stacked on-board QSFP and SFP cages and LEDs, with full control of the four ports through a single I2C or SPI interface. The on-board MSP430 controller and GUI allow for easy configuration and testing of the FPC401, and the headers allow for interfacing with an external host controller. The board also functions as a reference layout for placement of FPC401 underneath SFP+ cage.
Fig. 2 The FPC401EVM evaluation board (top side shown) allows for full exercise of the FPC401 via a PC's USB port and GUI; it also serves as a board-layout reference design.(Source: Texas Instruments)
For more information on the FPC401 Port Controller Aggregator, click here; for details on the FPC401EVM evaluation board, click here.
