We have been trying to shrink the size of electronic components since the start of the modern electronic era, in order to make our gadgets faster, smaller and cheaper. The transistor is the component that is used as a “measure” of our success. Transistors are the fundamental building blocks of all the electronics devices in the market. Transistor size is measured by the length of the gate. The gate is the most critical part of the transistor, making it possible for the device to switch “on” and “off.”
In 1970 we could fit two or three thousand transistors on a typical chip. Now we can put over one trillion, so today’s smartphones are more powerful than what were considered supercomputers 40 years ago, due to the fact that we have been able to shrink transistors continuously.
However,
Figure 1 according to the International Technology Roadmap for Semiconductors (ITRS), a group of chip giants that report about advancements in the performance of integrated circuits, starting in 2021 it will be impossible to continue shrinking the silicon transistor because it will not be economically viable to make them smaller. A modern transistor’s gate size is around 20 nanometers (nm), but by 2021 and beyond the size will remain at 10 nm, as shown in the accompanying figure.
This prediction, however, was debunked at the beginning of this month when a research team of engineers and scientists at the U.S. Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) announced the creation of the first transistor with a gate length of only 1 nanometer. This is an outstanding development.
“We made the smallest transistor reported to date," said Ali Javey, lead principal investigator of the Electronic Materials program in Berkeley Lab's Materials Science Division. "The gate length is considered a defining dimension of the transistor. We demonstrated a 1-nanometer-gate transistor, showing that with the choice of proper materials, there is a lot more room to shrink our electronics."
The researchers did not exclusively use silicon, instead utilizing a combination of nanotubes and molybdenum disulfide (MoS2). This latter material has great potential for LEDs, lasers and nanoscale transistors. MoS2 is simple lubricant for engines normally found in auto parts shops.
This finding could be what the industry has been waiting for to keep alive the Moore’s law prediction that the density of transistors in a chip will double every 18 – 24 months, assuring continuous improvement in the performance of our electronic gadgets.
"The semiconductor industry has long assumed that any gate below 5 nanometers wouldn't work, so anything below that was not even considered," said Sujay Desai, a graduate student in Javey's lab. "This research shows that sub-5-nanometer gates should not be discounted. Industry has been squeezing every last bit of capability out of silicon. By changing the material from silicon to MoS2, we can make a transistor with a gate that is just 1 nanometer in length, and operate it like a switch."
How did they do it?
The researchers noted some interesting electron behavior of electrons when a transistor’s gate is under 5 nm. Transistors consist of three main parts: the source, the drain and the gate. Electrons (current) flow from the source to the drain and the amount is controlled by the gate. The space between the source and the drain is called the channel of the transistor. By applying a proper voltage to the gate it can shut off the movement of electrons in the channel (the “off” condition of the transistor) or enhance it (the “on” condition), acting precicely as a controller switch.
Electrons moving in silicon are lighter – encounter less resistance – than electrons moving through MoS2. This is the case when the gate is 5 nm or longer; this is the reason silicon is a better performer for these lengths. When the gate is 5 nm or less, a quantum mechanical phenomenon (quantum tunneling) occurs. During quantum tunneling the gate can’t turn off the flow of electroncs from source to drain in silicon, and the current keeps flowing regardless of the voltage at the gate. In other words, in a silicon transistor the gate is useless if its length is 5 nm or less.
The Berkeley Lab researchers found that this is not the case when the conduction of electrons from source to drain takes place within a MoS2 channel. Because the electrons in this material are heavier – with more resistance – they found that turning “on” and “off” the flow of current can be accomplished with a smaller gate. At the same time, it is possible to make the channel thinner than normal with a lower dielectric constant. This in turn significantly lowers the strain capacitances inside the transistor, lowering the time delay and increasing its performance. The Berkeley Lab researchers developed a transistor with a gate length of 1 nm and a channel thickness of only 0.65 nm.
Figure 2. Schematic of a transistor with a molybdenum disulfide channel and 1-nanometer carbon nanotube gate. Credit: Sujay Desai/UC BerkeleyOnce they decided that they wanted to use MoS2 for the channel, they had to choose the material for the gate. To build a gate of only 1 nm is not a trivial proposition. Photolithography – the technique used to build all parts of silicon transistors – does not work at this scale. So they turned their attention to carbon nanotubes. These structures are hollow tubes of certain carbon strutures with diameters as small as 1 nm, and they can be manufactured without the need to use photolithography. This decision settled the development of the 1 nm gate.
"This work demonstrated the shortest transistor ever," said Javey, who is also a UC Berkeley professor of electrical engineering and computer sciences. "However, it's a proof of concept. We have not yet packed these transistors onto a chip, and we haven't done this billions of times over. We also have not developed self-aligned fabrication schemes for reducing parasitic resistances in the device. But this work is important to show that we are no longer limited to a 5-nanometer gate for our transistors. Moore's Law can continue a while longer by proper engineering of the semiconductor material and device architecture."
The second figure shows a schematic of the nanotube and MoS2 transistor.
The findings were published October 6, 2016 in the journal Science (http://science.sciencemag.org/content/354/6308/99). Other investigators on this paper include Jeff Bokor, a faculty senior scientist at Berkeley Lab and a professor at UC Berkeley; Chenming Hu, a professor at UC Berkeley; Moon Kim, a professor at the University of Texas at Dallas; and H.S. Philip Wong, a professor at Stanford University.
