Semiconductors and Components

Altera Releases Stratix 10 FPGA Details

16 June 2015

Altera reveals details about its next-generation Stratix 10 FGPAs and SoCs. Image source: Altera.comAltera reveals details about its next-generation Stratix 10 FGPAs and SoCs. Image source:

Altera Corp. has revealed architectural and product details of its next-generation Stratix 10 field programmable gate arrays (FPGAs) and system-on-chip (SoCs).

The programmable logic devices, built using Intel Corp.’s 14nm Tri-Gate process, provides a 2x higher core performance over Altera’s previous generation of FPGAs, the San Jose, Calif.-based company says. Stratix 10 is targeted at applications including communications, data center, Internet of Things (IoT) infrastructure, military and high-performance computing systems.

Stratix 10 is the first devices from Altera that will be based on its HyperFlex architecture that introduces registers throughout all core interconnect routing segments. This benefits the devices by enhancing certain design techniques such as register retiming, pipelining and other design optimization methods. Altera claims that these techniques are not practical in other manufacturing design processes and helps engineers eliminate critical paths and routing delays, speeding up the time it takes to design.

Other features include up to 5.5 million logic elements in a monolithic die, heterogeneous 3D SiP integration, up to 144 transceivers for 4x serial bandwidth over Altera’s previous generation, a 4-bit quad-core ARM Corex-A53 hard processor subsystem, hard floating point digital signal processor (DSP), secure device manager for security capabilities, single-event upset (SEU) detection and scrubbing and a footprint-compatible migration path from Altera’s Arria 10 FPGAs and SoCs.

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Related links:

IHS Semiconductors & Components

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