Semiconductors and Components

Altera Taps TMSC's Fine-Pitch Copper Packaging Technology

02 May 2014

production TSMC's patented, fine-pitch copper bump-based packaging technology.

Altera (San Jose, Calif.) said it worked with TSMC to bring the packaging technology to its Arria 10 FPGAs and SoCs.

"Leveraging this technology is a great complement to Arria 10 FPGAs and SoCs and helps us address the packaging challenges at the 20 nm node," said Bill Mazotti, vice president of worldwide operations and engineering at Altera, in a statement.

Altera also announced recently that it successfully demonstrated its FPGA technology based on Intel’s 14-nm tri-gate process and laid claim to being the first programmable logic company to integrate hardened IEEE 754-compliant, floating-point operators in an FPGA.

Altera said TSMC’s flip chip ball-grid array package technology would provide Arria 10 devices with better quality and reliability than standard copper bumping solutions through the use of fine-pitch copper bumps. The technology is able to accommodate very high bump counts as required by high-performance FPGAs, Altera said. The technology also provides other benefits, including superior bump joint fatigue life, improved performance in electro-migration current and low stress on extra low-K layers, Altera said.

Altera is now shipping 20-nm Arria 10 FPGAs with the TSMC packaging technology. The devices boast the FPGA industry’s highest density in a single monolithic die and up to 40 percent lower power than the previous 28 nm Arria family, according to Altera.

Altera said it demonstrated its 14-nm silicon on the Intel tri-gate process using test chips incorporating key intellectual property—including transceivers, mixed-signal IP and digital logic—used in the company's Stratix 10 FPGAs and SoCs. Intel is manufacturing Altera's 14-nm devices as part of a foundry services agreement. In March, Altera announced it would also work with Intel's assembly and packaging manufacturing lines to create heterogeneous multi-die systems that combine 14nm FinFET Stratix 10 FPGAs and SoCs with other ICs such as memories, processors and analog components.

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