Today’s biggest technology shifts are not only driven by new semiconductors, they are also driven by an often-overlooked component: IC substrates. AI, IoT, high-power modules, RFIC components and SiPs with diverse functions have not been fabricated on monolithic silicon for some time, and instead these are often produced using more advanced processes on a substrate. Following substrate fabrication and assembly, the chip is packaged and is sent off to customers.
An IC substrate is a very important component in IC packaging, which allows electrical connections to reach to the exterior of the chip and connect to a PCB. Despite the importance of these components, the design and production knowledge for these components is scattered across HDI/UHDI PCB design and integrated circuit packaging in general. As the technologies mentioned above continue their growth, substrate fabrication capacity will also need to increase to fill the required demand. This brings the issue of fabrication defects in IC substrate processing to the forefront, especially as new fabrication facilities come online.
Major copper defects
With IC substrates sitting somewhere between HDI PCBs and integrated circuits in terms of complexity (i.e., feature size), the processes used to fabricate IC substrates switch from subtractive etching to additive as feature size decreases. The small feature sizes and alternative processing leads to a specific set of potential defects in the deposited copper traces and vias. The primary types of copper defects include:
- Void formation
- Copper-on-copper defects
- Misalignment
Voids — These appear as empty regions within the copper layers of an IC substrate, which can be clearly seen in a cross-sectional image. They can be caused by various factors, including inconsistent electroplating, contamination or defects caused during lamination. Voids can be introduced during electroplating when the copper deposition is not uniform (e.g., from the edge effect and limited ion transfer) or when there are contaminants on the substrate surface.
Void detection can be challenging as it requires advanced high-resolution imaging systems and automated optical inspection (AOI) technologies for accurate identification and characterization. These systems must differentiate between voids and other surface imperfections to ensure reliable detection.
Copper-on-copper defects — Copper-on-copper defects can occur on dense copper patterns above a copper base (seed) layer. These defects can start as mechanical defects, but they produce an electrical defect (e.g., short or open circuit).
Organic substrate materials can mask the presence of copper-on-copper defects due to the lack of contrast between the defect morphology and the substrate material. This has made identification of defects quite difficult, which demands facilities implement state-of-the-art AOI systems with high resolution.
Misalignment — Inaccuracies in photolithography process, shifting of substrate layers during processing or equipment misalignment can lead to layer-to-layer misalignment (better known as “misregistration” among PCB manufacturers). The result is missed drill hits at specific points in the substrate or incorrect formation of copper traces in neighboring layers (e.g., during photolithography), both of which are problematic for via formation. Misalignment could produce up to ~1 million of misregistration errors, which could be unacceptably large for the small via and pad diameters used in substrates.
Process control steps that address defects
Each portion of the fabrication process demands precision control in order to address copper defects in IC substrates. The major processes involved in IC substrate fabrication are:
Copper electroplating - involves depositing a uniform layer of copper onto the patterned substrate, followed by immersion in a plating solution containing copper ions. The goal is to achieve controlled, uniform growth of the copper layer for optimal performance.
- Photoresist coating — application of photoresist is required to mask areas of the substrate where copper traces will be formed. The photoresist will then be exposed and cured to form a mask.
- Photoresist removal — following exposure and copper deposition/formation, the photoresist is stripped and reclaimed.
- Laser drilling — vias are formed with a laser drilling process that enables very small diameter vertical interconnects between layers. Subsequent desmear, plating and cleaning steps will complete the drilling process.
- Layer stacking and curing — after fabrication and cleaning, the buildup layers are stacked and cured to form the completed IC substrate.
During electroplating, several issues can lead to defects in the copper layer, including non-uniform deposition caused by variations in the electric field or chemical concentration, contamination from the plating bath and hydrogen embrittlement, which can lead to brittleness and micro-cracks. Additionally, the quality of the photoresist used in copper patterning is crucial, as poor photoresist can result in defects during removal, such as incomplete removal or mechanical damage to the copper traces. The curing process, which bonds the buildup film to the substrate, must also be carefully controlled, as improper curing can cause voids or thermal stress, potentially leading to warping, delamination or reduced electrical performance.
In summary, the table below offers an overview of the process control areas where copper defects can arise in IC substrate fabrication.
By understanding the causes of copper defects in IC substrate fabrication, manufacturers can implement targeted process controls and inspection techniques to minimize these defects, ensuring high-quality and reliable IC substrates. As advanced PCB manufacturers in North America and Europe prepare to serve a growing packaging market, they will need to develop their expertise in these areas to ensure high-quality copper fabrication in IC substrates.
