Applied Materials has unveiled at SEMICON West 2024 materials innovations designed to increase the performance-per-watt of systems by enabling copper wiring to scale to the 2 nm logic node and below.
The company has introduced a new version of its Black Diamond material — used to reduce buildup of electrical charges in surrounding copper wires in a design — that reduces the minimum low-dielectric constant (k-value) to enable scaling to 2 nm and below. Applied Materials said this material also offers increased mechanical strength to take 3D logic and memory stacking to new sectors.
Applied Materials added that the technology is already being adopted by logic and DRAM chipmakers.
“The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption,” said Prabu Raja, president of the semiconductor products group at Applied Materials. “Applied’s newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights.”
Integrated materials
Applied Materials has also introduced the latest integrated materials solution that combines six different technologies into one vacuum system. This technology includes a binary metal combination of ruthenium and cobalt (RuCo) that allows semiconductor vendors to scale copper wiring to the 2 nm node and below. This technology:
- Reduces the thickness of the liner by 33% to 2 nm
- Produces better surface properties for void-free cooper reflow
- Reduces electrical line resistance by up to 25%
Called Applied Endura Copper Barrier Seed IMS with Volta Ruthenium CVD, the integrated materials solution is being adopted by logic chipmakers with some working on 3 nm node already, Applied Materials said.
Why it is needed
Logic chips contain tens of billions of transistors that connect more than 60 miles of microscopic copper wiring. Each of these wirings begins with a thin film of dielectric materials that is etched to create channels filled with copper.
While this technology has been the mainstay of wiring for decades, as process technology scales to 2 nm and below, thinner dielectric material renders chips weaker with narrowing the copper wires creates steep increases in electrical resistance. This can reduce the performance and increase the power consumption of semiconductors.
SEMICON West 2024 takes place this week in San Francisco, California.
