Power Semiconductors

Heterogeneous integration means companies can take chip designs in-house

15 November 2023
Heterogeneous integration in advanced processors is allowing companies to take the lead on system-in-package and other advanced packaging options. Source: Anoo/Adobe Stock

For decades, companies that needed an advanced processor were stuck with whatever a semiconductor manufacturer could provide on monolithic silicon. Looking back to the late 1990s and early 2000s, chips were bulky and obtaining a custom processor was an expensive endeavor. If you wanted a custom processor for your system, design expertise was needed, and the product would only be commercially viable at high volume.

Today, companies have more options, both for off-the-shelf processors and custom chipsets for advanced devices. Over the past 20 years, packaging design methodologies and the expansion of foundry capacity have shifted the dynamics of chip design and production for systems engineers. Now there is a perfect storm of widely available IP, access to foundry services, access to OSAT capacity, standardized workflows with PDKs and standardized packaging constructions that make custom packages easier to access.

Easier custom design

Now that the design world has moved away from monolithic silicon and into heterogeneous integration, more companies are taking ownership of their SoC designs with advanced packaging techniques. The current environment for packaging designers is a perfect storm for companies that want to pursue custom chip design for their new products:

  • Many packaging techniques are standardized and are available at volume
  • RISC-V as an ISA and RISC-V-enabled cores offer an alternative to Arm and x86/x64
  • Foundry capacity is increasing and on-site packaging capabilities are growing
  • An expanding chiplet ecosystem offers greater access to capabilities and features
  • Interface IP is readily available under license

With all these factors in play, it should be no surprise that more companies are bringing chip design and engineering in-house. Heterogeneous integration gives systems engineers much more control over the features and functions their products can provide. Component designers can mix-and-match features by selecting multiple dies with required IP for their components, then the challenge becomes one of designing packaging to the correct specifications.

Matching package to application

Systems designers that want to build custom chips as heterogeneously integrated components should know more about the typical applications for different types of packaging. Over the past decade, chip design has gone from single-die on an organic/ceramic substrate to complex stacks

Today’s common advanced packages that enable heterogenous integration of diverse chiplets are summarized above. Most notably, 2D integration has still not gone away and is appropriate for many SoCs, even those targeting advanced areas like 5G and AI.

The above packaging methods are typically chosen based on the ability to integrate the diverse functions needed for specific applications. For example, advanced high-compute processors that need a lot of high-bandwidth memory (HBM) need to be built in EMIB packaging, whereas a more diverse SoC may only need InFO-PoP or DSMBGA packaging. In a broad sense, the typical application areas for these packaging technologies includes:

  • FOWLP, WLCSP — and EWLBGA — Fine-pitch components
  • InFO-PoP — Mobile processors with in-package memory
  • DSMBGA — SoCs with diverse functions
  • EMIB — High-compute processors in AI, HPC

Challenges ahead

When companies make the move to in-house component design and packaging design, there are several challenges that arise. Aside from workflow and collaboration with internal teams and vendors, there are three major areas where design teams may struggle:

Higher bandwidth channels — Not all new components will be operating at the fastest data rates, but for those that are working far above 25 Gbps SerDes, package geometry limits channel bandwidths. This is a well-known problem among HDI PCB designers who work with fine-pitch FPGAs that have many SerDes interfaces. The biggest challenge is found in the vertical via transitions in RDL routing and in skip-layer routing transitions to the ball-out on the bottom of the package. The bandwidth limiting found in vertical transitions may drive the following design requirements:

  • Lower Dk substrates are normally needed
  • Smaller diameter vias are normally needed
  • Smaller via pitch is sometimes needed

First, in the area of simulation and evaluation prior to sign-off, simulation difficulties arise due to the structure of packages, which requires 3D electromagnetic simulation packages to understand electromagnetic wave propagation in the RDL and skip-layer routing. The other important area is die modeling for power and I/Os; vendors provide die models that describe the equivalent circuit characteristics which can be used in IC simulators. It is well-known that these models are not always accurate, and some evaluation of die models is often needed.

Secondly, in the area of reliability, packaging construction needs to be proven to be reliable in envisioned deployment environments. Reliability in packaging is an ongoing challenge and certain problems arise in different packages. For example, in EMIB, the reliability of through-silicon vias (TSVs) is a major problem, while in InFO-PoP the CTE mismatch across materials is a greater challenge. Thermomechanical simulations and thorough testing are needed to prove reliability in many new chip designs.


The industry continues to develop integrated design suites and simulation-driven design flows to address these problems. The biggest challenges surrounding these packages can be addressed with software, but ultimately a robust internal process can help companies overcome these challenges and take ownership of their package designs.

To contact the author of this article, email GlobalSpecEditors@globalspec.com

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