Achronix Semiconductor Corp. and Mentor Graphics, a Siemens company, have unveiled a high-level synthesis (HLS) flow for field programmable gate array (FPGA) devices.
The integrated development environment allows designs to go from C++ to FPGA using Mentor’s Catapult HLS and Achronix’s ACE design tools. The technology was originally used for 5G wireless applications to reduce development effort and quality of results (QoR) but is suitable for any design targeting Achronix’s FPGA technology, the companies said.
The Catapult HLS to Speedcore embedded FPGA technology flow allows designers to make changes in late stages of intellectual property (IP) development in order to optimize the algorithm and the digital micro-architecture. The verification environment allows reuse of the software tests for generated register transfer level (RTL) code, which helps reduce the need for dedicated RTL test benches by more than 80 percent, the companies said.
The Achronix FPGA technology can be used to accelerate hardware used in data center computing, networking and storage, 5G wireless infrastructure, network acceleration, advanced driver assistance systems (ADAS) and autonomous vehicles.
Early versions of the design and development environment are available now.