Memory and Storage

The rise of 3D NAND flash memory

24 August 2022
3D NAND flash memory has made the market for solid state drives explode and has become a primary storage unit for many applications. Source: AdobeStock/Rmcarvalhobsb

Memory chip costs are typically based on the area of each chip, naturally, the greater density of bits on a chip, the cheaper the price per bit. As memory storage devices become smaller, new technologies can be realized at lower cost.

3D NAND offers greater storage capacity than its predecessors for the same size of chip and has had a profound effect on consumer markets. Memory prices have continued to decrease since their inception as more cost-effective technologies were developed.

The evolution of flash memory

Floating-gate transistors were invented at Bell Labs in 1959 by Mohamed M. Atalla and Dawon Kahng. Building upon this invention, a new type of floating-gate memory, called flash memory, was proposed by Fujio Masuoka while working at Toshiba in 1980. With flash memory, entire sections of memory could be erased simply by applying a voltage to a single wire. Initially presented as NOR flash in 1984 and then NAND flash in 1987, Toshiba commercially released NAND flash memory in 1987, and it has come a long way since then.

NAND flash memory uses floating gate transistors with multiple gates to store data. It is a type of non-volatile computer memory that can be electrically erased and reprogrammed in units called cells. It can hold memory even if not connected to a power source. NAND is short for “NOT AND” and on a circuit level NAND flash memory behaves similarly to the NAND logic function.

There are three basic types of flash memory: Single level cell (SLC), multi-level cell (MLC) and tri-level cell (TLC). SLC flash memory stores one bit per cell. MLC flash memory stores 2 bits per cell. TLC flash memory stores 3 bits per cell and 3D NAND or, quad-level cell (QLC) NAND can store up to 4 bits per cell.

In flash memory’s first and simplest form, SLC NAND, a single bit of data is stored in each cell. The transistor is programmed by applying a voltage to the transistor's gate, which causes electrons to tunnel through the oxide between the floating gate and the substrate. This changes the threshold voltage of the transistor and allows it to be read as either 1 or 0. Subsequent versions of flash memory have more threshold voltages allowing for more bits to be stored per cell.

Flash memory uses semiconductor cells instead of ferromagnetic polarization concepts used in hard disk drives (HDD). HDDs theoretically allow for an unlimited number of read and writes as long as the mechanical components are still operational. On the other hand, while flash memory does not have moving parts, it still has limitations to the number of writes. Flash memory is written in blocks and performing a read function is straightforward with the address being issued and the corresponding stored data being returned. HDDs can overwrite data while a write command in flash memory requires an erased available block, this erase cycle before writing data is what wears out the cells and causes them to degrade until they are unusable.

Trending to fewer writes per day

SLC flash devices typically have the highest endurance with 100,000 cycles, while QLC flash devices have significantly less endurance of around 1,000 cycles. Previously, drive writes per day (DWPD) was used to describe the endurance of memory storage, but with QLC this measurement holds less weight than a more descriptive property such as terabytes written (TBW). Instead of measuring how many times a cell can be overwritten, determining how many terabytes can be written in the hard drive's lifespan would be a more relevant measurement.

DWPD is a measure relative to drive size. A 480 GB SSD with a 64 DWPD would have an equivalent TBW rating of 56064 as a 30.72 TB SSD only rated at 1 DWPD. While 1 DWPD seems like an awful rating, the TBW are the same for both examples. Tight tolerances on the charge levels needed at each state in a memory cell is a contributing factor to the lower endurance of 3D NAND.

Difference between QLC and TLC NAND

When manufacturing 3D NAND, it is difficult to manufacture features, such as floating gates and sideways, which is necessary for 3D NAND. As a result, QLC predominantly uses charge traps instead of floating gates commonly used in TLC. Charge traps are insulators while floating gates are conductors.

Flash memory uses electrical charge trapped on an insulated layer to store data. Charge trap flash (CTF) replaces conducting polysilicon with insulating nitride. CTF is less prone to electron leakage, though electrons can still become trapped in the nitride and lead to degradation. Higher temperatures exacerbate electron leakage as electrons become more excited.

TLC holds eight states per floating gate while QLC hold twice that, at 16. As a result, the threshold differences between each layer are almost halved in QLC, which increases the exposure to noise and process variances. New applications in artificial intelligence (AI) coupled with machine learning dampen some of the ill-effects of circuit level noise in 3D NAND memory. The storage capacity in QLC has led many all-flash array manufacturers to augment their controller software to mitigate much of the drawbacks in CTF.

Charge traps also require lower amounts of voltage than floating gates, this lower programming voltage gives charge trap flash greater endurance. A charge trap also improves reliability in 3D NAND, as each threshold voltage has little variance, the insulator properties of a charge trap prevent charge from floating from one side to another. As a result, the bit would be less likely to fail if there is a defect point in the tunnel oxide layer when compared to conventional floating gate flash. Both reduced oxide stress, and greater resiliency to single point defects improve reliability.

Storage technology should always be matched to the application at hand. For example, SLC has high performance capabilities but also has a high cost per bit and is best suited for critical, embedded systems, and industrial device applications. As SLC and MLC are the fastest, most reliable, and most expensive drives, they are more widely used in enterprise applications. Lower end consumer products benefit from TLC and are not suited for frequent data updating.

Beyond 3D NAND

Flash memory will inevitably hit a scaling limit. Once that limit is reached, successor technologies will have to displace flash memory and may be based on completely different and undiscovered technologies. To the consumer, this change will have little effect, perhaps the greatest effect will be felt by SSD controller designers. As flash exclusive fundamentals such as error correction algorithms, garbage collection, wear levelling and write acceleration would become obsolete.

About the author

Jody Dascalu is a freelance writer in the technology and engineering niche. She studied in Canada and earned a bachelor’s degree of engineering. Jody has over five years of progressive supply chain work experience and is a business analyst. As an avid reader, she loves to research upcoming technologies and is an expert on a variety of topics.

To contact the author of this article, email

Powered by CR4, the Engineering Community

Discussion – 0 comments

By posting a comment you confirm that you have read and accept our Posting Rules and Terms of Use.
Engineering Newsletter Signup
Get the GlobalSpec
Stay up to date on:
Features the top stories, latest news, charts, insights and more on the end-to-end electronics value chain.
Weekly Newsletter
Get news, research, and analysis
on the Electronics industry in your
inbox every week - for FREE
Sign up for our FREE eNewsletter