Five important questions to ask when designing ESD protection for mobile and wearable devices
Use the latest circuit protection and PC board layout tips when designing for the best electrostatic discharge (ESD) suppression to protect devices from their worst enemy — the end-users.
Consumers who wear vision correction glasses are used to seeing the world through lenses. Today’s new technologies are allowing a virtual world to be layered on top of the real-world using augmented reality (AR) glasses. The lenses become intelligent displays, allowing users to see the “real” world augmented with useful overlaid information and images. An example would be the integration of navigation into the AR glasses to allow a user to walk through a city with step-by-step directions (visual or verbal) to help them get to their destination. Other AR examples include facial recognition, fitness tracking/health-sensing, travel assistance, real-time news, first-person pictures and videos (Figure 1).
Whether a design engineer is creating a mobile device or wearable that is incorporating AR, it is important to be aware of the advanced circuit protection solutions and board layout strategies that safeguard these highly valued devices and their end-users. By reviewing and answering these five questions and applying the answers early in the electronics design process, circuit designers will improve the overall performance, reliability and safety of their mobile and wearable designs and help build a more reliable IoT ecosystem.
1. Smaller form factors: How small is small enough?
ESD diodes offer electronics designers a variety of performance benefits for mobile and wearables applications requiring increasingly smaller form factors (Figure 2). To optimize their circuit designs, designers should follow these recommendations for both the selection and configuration of ESD diode technologies.
2. Choosing the right ESD diode: Unidirectional or bidirectional?
There are two diode configurations available for ESD protection — bidirectional and unidirectional. Use unidirectional diodes for DC circuits, including pushbuttons, keypads and other digital circuits. Use bidirectional diodes in AC circuits that may include any signal with a negative component greater than -0.7 V. These circuits include audio, analog video, legacy data ports and RF interfaces.
Where possible, electronics engineers should choose unidirectional diode configurations to improve performance during negative-voltage ESD strikes. During these strikes, the clamping voltage is based on the forward bias of the diode, which is usually less than 1.0 V. During a negative strike that is based on the reverse breakdown voltage, a bidirectional diode configuration provides a clamping voltage that is higher than the forward bias of a unidirectional diode. Thus, the unidirectional configuration dramatically reduces the system stress experienced during negative transients.
3. Where should the ESD diode(s) be located for maximum effectiveness?
Board-level ESD diodes at each of the IC’s pins are not required in most circuits. Instead, determine which pins could be exposed to user-generated ESD events that occur outside of the application. For example: If the communications or control line can be touched by the end-user, then it becomes a possible ESD pathway to enter the sensitive integrated circuits. Typical user interface circuits include switches, buttons, USB, audio and other data buses. To avoid using too much board space, it is important to reduce the size to fit 0201 or 01005 footprints while incrementally adding these discrete devices. There are also space-saving multi-channel arrays available for many wearable applications. Place the ESD protection device as close as possible to the ESD ingress point, which is typically the connector or the I/O.
4. What are the “ESD” trace routing considerations?
To protect the IC’s pins with an ESD diode, there are several key considerations for trace routing — from I/O to ground. Unlike lightning transients, ESD does not unleash a significant amount of current for an extended duration of time. It is important to move the charge from the protected circuit to the ESD reference as quickly as possible to effectively handle ESD. The length of the trace — from the I/O line to the ESD component and from the ESD component to ground — are the overriding factor, not the width of the trace to ground. Limit parasitic inductance by keeping the trace lengths as short as possible. If the stub trace is too short, this inductance results in inductive overshoot, which is a brief voltage spike that can reach hundreds of volts. Package developments, including µDFN and Wafer Level Chip Scale Packages (WLCSP), utilize outlines that fit directly over the data lines to completely eliminate the need for stub traces.
5. Why are HBM, Machine Model (MM) and Charged Device Model (CDM) definitions important?
There are several test models for characterizing the ESD robustness of the integrated circuits that run mobile and wearable devices, including the processor, memory and ASIC. HBM, MM and CDM are used by semiconductor suppliers to ensure the robustness of the design’s circuitry during manufacturing. Currently, the trend is for suppliers to reduce the voltage test levels since it saves die space. Most electronics manufacturers will not only provide for ESD protection, they also have countermeasures in place during the product’s assembly process.
If ESD protection only becomes a consideration during assembly, then once the device reaches the consumer, the device is susceptible to ESD damage in the end user’s environment. Without adequate built-in ESD countermeasures, electronic devices will fail incrementally or catastrophically in the user’s environment. To guarantee fewer ESD-related field failures and thus ensure happy customers, electronics design engineers should select a robust board-level device that protects against intense electrical stresses, yet offers the bandwidth and the electrical performance demanded by the end-user applications.
When evaluating ESD protection components, consider the following parameters:
- Dynamic resistance: Defines the diode’s resistance to the change in state from blocker to conduit of electronic energy. This value represents how quickly the diode will clamp and divert the ESD transient pulse to ground. It helps define how efficiently the avalanche diode conducts the excess voltage and current to ground. The more vertical the I-V or TLP curve is, the more efficient the avalanche diode is, and the lower the expressed dynamic resistance.
- IEC 61000-4-2 rating: Tested and confirmed during design and characterization, this rating reflects what the ESD diode is capable of withstanding repeatedly without degradation of the DC performance. For this parameter, the higher the value, the better. An increasing number of ESD diodes available from Littelfuse approach 20 kV and 30 kV under contact discharge conditions, which regularly exceeds industry standards for fielded electronics, nominally 8 kV air discharge.
- DC (direct current) performance: Remember these important considerations when designing circuits that need protection:
- Parasitic capacitance,
- Parasitic inductance,
- Surge tolerance (8/20 us), and
- Nominal and maximum leakage currents.
The approach will vary depending upon the performance characteristics of the interfaces being protected.
Download a copy of the white paper Five Important ESD Protection Considerations for Augmented Reality Wearables, courtesy of Littelfuse, Inc.