Memory and Storage

Microchip enters memory infrastructure market

06 August 2019

The PM8596 serial memory controller. Source: Microchip TechnologyThe PM8596 serial memory controller. Source: Microchip TechnologyMicrochip Technology Inc. has entered into the memory infrastructure market with the introduction of its serial memory controller.

The SMC 1000 8x25G allows central processing units (CPUs) and other computer-centric system-on-chips (SoCs) to use four times the memory channels of parallel attached DDR4 dynamic random access memory (DRAM) in the same package footprint. Microchip said the memory allows these compute-intensive platforms to have higher memory bandwidth with low latency.

The serial memory controller interfaces to the CPU via 8 bit open memory interface (OMI)-compliant 25 Gbps lanes and bridges to memory via a 72 bit DDR4 3200 interface. This results in a reduction in the required number of host CPU or SoC pins per DDR4 memory channel, allowing for more memory channels and increasing the memory bandwidth.

Other features include a design that delivers less than 4 ns incremental latency over a traditional integrated DDR controller with load reduced dual in-line memory module (LRDIMM). This results in OMI-based dual in-line memory module (DDIMM) products having virtually identical bandwidth and latency performance to comparable LRDIMM products, Microchip said.

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