Industrial Electronics

App Note Demonstrates How to Utilize Fail-Safe Biasing in GaN Transistors

06 November 2018

Integra Technologies, a designer and supplier of high-power RF power transistors and RF power modules, has published an application note on how to best utilize the fully automatic and fail-safe bias circuit feature in their line of high power GaN transistors that only requires a single positive voltage power supply.

As GaN HEMT transistors are depletion mode devices ― requiring a negative voltage for the gate and a Source: Integra TechnologiesSource: Integra Technologiespositive voltage for the drain ― this dual voltage requirement can raise havoc when reducing biasing circuitry is an objective. Additionally, since they are depletion mode devices, it is critically important to supply the negative voltage to the gate before any positive voltage is applied to the drain, as the transistor will inherently draw its maximum possible drain current from the supply. This leads to excessive thermal dissipation and device burnout. For these reasons, Integra developed a fully automatic and fail-safe bias circuit for its GaN transistors that only requires a single positive voltage power supply.

Integra’s Application Note 004 “Automatic & Fail-Safe Biasing of GaN Transistors” describes how a diode detector connected to a coupler is used to sense when an RF signal is applied to the transistor. There are two stages of operation for this circuit. In the initial phase, a negative voltage is applied to the gate of the GaN transistor such that when the drain bias is subsequently applied, then the device will be bi­ased at pinch-off. In other words, no drain current will flow save for the finite leakage current of the transistor as specified in the transistor’s data sheet. The bias sequence of first apply­ing a negative gate voltage followed by the application of the positive drain bias is fail-safe, fully automatic and controlled by the circuit. Integra refers to this circuit as a gate pulsing and sequencing (GPS) circuit, and this first phase of operation is the sequencing aspect.

There are many important points to note about using the GPS circuit. One is that there is a finite delay between the application of an RF pulse at the input and the GaN device turning on, and likewise for the turn-off sequence. These delays and associated rise and fall times are detailed in the application note. Another point is that the circuit has a very beneficial effect on reducing the amount of shot noise injected into the receiver during the RF-off period. Additional details detailed in the application note include a presentation of time delay and rise/fall time measurements showing the circuit suppressing the output noise in the RF-off period by greater than 30 dB for a 500 W GaN transistor biased with a quiescent current of 200 mA.

High power amplifier designers will learn the advantages and operations of these circuits, and temperature compensation details are required for effective utilization of these innovative GaN transistors.

Download the application note “Automatic & Fail-Safe Biasing of GaN Transistors” and contact Integra's technical support team with any questions regarding GaN transistors.

To contact the author of this article, email engineering360editors@globalspec.com


Powered by CR4, the Engineering Community

Discussion – 0 comments

By posting a comment you confirm that you have read and accept our Posting Rules and Terms of Use.
Engineering Newsletter Signup
Get the Engineering360
Stay up to date on:
Features the top stories, latest news, charts, insights and more on the end-to-end electronics value chain.
Advertisement
Weekly Newsletter
Get news, research, and analysis
on the Electronics industry in your
inbox every week - for FREE
Sign up for our FREE eNewsletter
Advertisement
Find Free Electronics Datasheets
Advertisement