Silicon Labs has introduced a new family of multi-channel jitter attenuating clocks for 4.5-generation and Ethernet-based Common Public Radio Interface (eCPRI) wireless applications.
The Si5381/82/86 clocks use Silicon Labs’ DSPLL technology for advancing timing that combines fourth-generation/long-term evolution and Ethernet clocking in a single integrated circuit (IC). The clocks eliminate the need for multiple clock devices and voltage controlled crystal oscillators.
These ICs work in applications such as small cells, distributed antenna systems (DAS), micro-buddy tracking system baseband units (BBU) and fronthaul/backhaul equipment.
The clocks are optimized to provide reference timing for HetNet equipment and the low-phase-noise DSPLL, replace a discrete clock IC, VCXO and loop filter components in a compact, single-chip design. The Si5386 clock integrates five MultiSynth fractional clock synthesizers to provide simplified Ethernet and baseband reference timing proving an alternative for solutions that rely on multiple phased-locked loops and discrete oscillators.
The Si538x family is sampling now with production planned for availability in December priced at $6.77 for the Si5386 clock in 10,000 unit quantities.