Hafnium dioxide, best known as the insulator material used for high-k metal-gate (HKMG) transistor structures, could find additional use as the basis of a scalable ferroelectric memory, according to research results from a collaborative project between the NaMLab at Technical University of Dresden, Fraunhofer Institute for Photonic Micro Systems (IPMS) and Globalfoundries Inc. (Santa Clara, Calif.), which has a wafer fab in Dresden.
The research is part of the five-year Cool Silicon collaborative funding scheme for research in the Dresden area and the progress in characterizing ferroelectricity in hafnium oxide has made it into the current version of The International Technology Roadmap for Semiconductors.
Professor Thomas Mikolajick, director of the NaMLab at TU Dresden, said that compared to current-driven non-volatile memory (NVM) such as magnetic RAM, resistive RAM and phase-change RAM, the field-driven ferroelectic RAM has faster speed of switching and lower power consumption.
FRAM has been deployed for many years but the implementation has been based on the use of perovskite materials – typically lead zirconate titanate (PZT) or strontium bismuth tantalate (SBT) – and these materials have issues related to integration with CMOS manufacturing, and with scaling due to the thick films required. The inability to scale FRAM below about the 0.25-micron node has been one of the reasons MRAM, ReRAM and PCRAM have been pursued in many forms as a means to replace the charge-based DRAM and flash memory, which are now coming to scaling limits, Professor Mikolajick told Electronics 360.
The Dresden work is based on a discovery made in research at now-defunct DRAM manufacturer Qimonda in 2007 by Tim Boeske. He foumd that hafnium dioxide, if treated correctly could be made ferroelectric, said Professor Mikolajick. "And doping with silicon atoms is the easiest way to do this so that we achieve the orthorhombic phase of the hafnium dioxide lattice," he added.
Schematic representation of orthorhombic phase of certain Si:HfO2 composition. Source: NaMLab.
The Cool Memory project, a sub-project of Cool Silicon has developed a HfO2-based ferroelectric non-volatile memory chip that requires low write voltage, and can be produced at 28nm and whose production can easily be integrated in common semiconductor manufacturing processes.
So far the group has built passive arrays of about 100 transistors for testing purposes. In isolation the ferroelectric HfO2 material showed an endurance of 10^10 cycles although in the transistor arrays this was reduced to 10^5. "This is due to charge-trapping and there are things we can do to reduce the this in terms of the field distribution," said Professor Mikolajick.
Hafnium oxide, which is a transition metal oxide, has also been the subject of resistive RAM research, particularly at the IMEC research institute at Leuven, Belgium. "The physical effect is different. With ReRAM you are moving oxygen vacancies through an insulator to make a filament that you can then switch on and off at the weakest point," Professor Mikolajick said. With ferroelectric RAM, while some of the mechanisms are not completely understood, it is thought that a field effect causes a shift of the crystal lattice to a different phase and different ferroelectric polarization.
The ferroelectric properties are caused for certain Si:HfO2 compositions by the appearance of a non-centro-symmetric orthorhombic phase under mechanical confinement at the boundary between the monoclinic and the tetragonal phases. Implementing this material in a FeFET transistor results in a memory device, which shows a threshold voltage shift of approximately 1.2 V depending on the polarization state of the ferroelectric material. Extrapolation of the measured memory window over time indicates that after 10 years still a window of 0.7 V is visible.
Cross-section of 32nm Si:HfO2-based MFIS-FET device. Source: Ekaterina Yurchuk et al., IEEE Transactions on Electron Devices, November 2014.
"The Cool Memory project is not over, We next want to integrate with peripheral circuits and create active arrays. We want to extend the project to a wider group of participants," said Professor Mikolajick. "If everything goes well we could be in time for 28nm NVM. As an academic at a research institute the timing is not up to me. It depends on the partners but we could be there in three to five years."
When challenged that taking three to five years to provide an embedded NVM for 28nm CMOS might be too late Professor Mikolajick countered by saying. "The mainstream for embedded NVM is at 65nm with 40nm in research."
Globalfoundries invests in Everspin
That may be so, but Globalfoundries is also backing the development of MRAM as a NVM option.
Globalfoundries has agreed to make magnetic tunnel junction (MTJ) Spin-Torque Magnetoresistive Random-Access Memory (ST-MRAM) technology on 40nm and 28nm low-power CMOS for Everspin Technologies Inc. (Chandler, Ariz.) and has invested an undisclosed amount of money in the company.
Everspin, formed as a spin out from Freescale Semiconductor Inc. In June 2008, has shipped 40 million MRAM and ST-MRAM chips in to data center, industrial, automotive, and transportation markets.
The hook up with Globalfoundries, which starts at the 40nm node, will allow Everspin to manufacture its ST-MRAM more competitively on 300mm-diameter wafers. For now the partnership appears focused on supplying stand-alone ST-MRAM components rather than providing MRAM as an embedded option.
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