Intel and IBM will each provide details of their respective 14nm manufacturing processes at this year's International Electron Devices Meeting (IEDM) to be held Dec. 15 to 17, 2014 in San Francisco.
Intel, which is already manufacturing chips based on the "Broadwell" micro-architecture using its 14nm FinFET process will report on technical features including low concentration doping of fins, resulting in reduced variability, two levels of air-gap-insulated electrical interconnects at 80nm and 160nm minimum pitches yielding a 17 percent reduction in capacitance delays; eight layers of 52nm pitch interconnects embedded in low-k dielectrics; and an embedded 140Mbit SRAM memory with a cell size of 0.0588 square microns. The 14nm transistors operate with a supply voltage of 0.7 volts.
The researchers also will discuss how the use of aggressive design rules enabled the production of fins 8nm wide and 42nm high that are more rectangular than the first generation 22nm fins, which were more triangular in cross-section (see Fins Ain't What They Used To Be).
In the same session IBM will describe a 14nm FinFET manufacturing technology based on a silicon-on-insulator (SOI) substrate. Although SOI is a more expensive starting point it simplifies manufacturing in terms of device isolation and allows finer control of threshold voltages. according proponents of the technology. IBM's 14nm FinFET-on-SOI transistors are more than 35 percent faster than IBM’s 22nm planar transistors, and can operate at a voltage of 0.8 volts.
IBM, which has announced the sale of its chip business to Globalfoundries, is manufacturing ASICs and server processors on a 22nm SOI process that is ramping to volume at present. The 14nm FinFET-on-SOI process is the next generation process that Globalfoundries will inherit and use to make server processors for IBM (see IBM To Pay Globalfoundries $1.5 Billion to Take Chip Business).
One of the attributes of the FinFET-on-SOI process is that it allows the inclusion of extremely dense embedded DRAM alongside logic. IBM is set to report an embedded DRAM memory cell size of 0.0174 square microns that provides high-speed read and write performance in an integrated manufacturing process.
IBM also set to report on how it can tune transistors implemented using the process for either low-power or high-speed. This is done by optimizing threshold voltages of both NMOS and PMOS transistors without degrading carrier mobility in the transistor channel.
The IBM design also features a record 15 levels of copper interconnection. Although leading-edge processes now use copper interconnect it is usually only for the lowest two or three levels with the rest of the interconnections made using aluminum.
Related links and articles:
Paper #3.7, "A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588µm2 SRAM Cell Size." S. Natarajan et al, Intel
Paper #3.8, "High Performance 14nm SOI FinFET CMOS Technology with 0.0174µm2 Embedded DRAM and 15 Levels of Cu Metallization," C.-H. Lin et al, IBM