Samsung has started mass production of a 128Gbit NAND flash memory that offers 3-bit multi-level cells and has 32 layers of memory in the vertical direction.
The vertical NAND memory (V-NAND), which Samsung revealed at the time of the launch of some solid-state drives in June 2014, is intended primarily, if not exclusively for use with solid-state drives (see Samsung Pushes Vertical NAND to 32 Layers).
At the time of the launch of the drives Samsung said that the V-NAND technology had been extended to 32 layers from the previous maximum of 24 but did not provide any engineering detail. In Samsung's V-NAND chip structure, each cell is electrically connected to a non-conductive layer using charge trap flash (CTF) technology
Samsung introduced its first generation V-NAND (24 layer cells) in August 2013, and introduced its second generation V-NAND (32-layer) cell array structure in May 2014, presumably without MLC capability. Now Samsung has a 32-layer, 3-bit V-NAND. All three generations of V-NAND have had 128-Gbit memory capacity in total, which is about the limit of a planar NAND flash memory in 10nm-class production.
The result of increasing the layers and adding 3-bit per cell MLC capability is to allow Samsung to relax the design rules on each plane thereby improving yield and preventing the need for double patterning lithography, which increases dwell time of wafers on manufacturing machines.
Samsung has not revealed what manufacturing process node it has used for the manufacturing but said that the use of 3 bit-per-cell, 32-layer vertically stacked cell arrays raises the efficiency of memory production. Compared to Samsung’s 10 nanometer-class 3-bit planar NAND flash, the new 3-bit V-NAND has more than doubled wafer productivity. The 10nm class label is used to denote a feature size of somewhere between 10nm and 19nm.
"With the addition of a whole new line of high density SSDs that is both performance- and value-driven, we believe the 3-bit V-NAND will accelerate the transition of data storage devices from hard disk drives to SSDs," said Jaesoo Han, senior vice president responsible for memory sales and marketing at Samsung Electronics, in a statement.
Samsung did not discuss how the move to 3-bit MLC in 32-layer V-NAND affects memory cycling endurance which diminishes with minimum geometries.
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