ISSCC: Toshiba Reduces SRAM Leakage

12 February 2014

Toshiba Corp. has developed a low-leakage 65nm SRAM suitable for use in back-up memory alongside low-power microcontrollers.

An advantage of the SRAM, which Toshiba calls XLL for eXtremely Low-Leakage, is that it can be ready for action quickly from a deep-sleep mode. Toshiba presented the development at the 2014 IEEE International Solid-State Circuits Conference in San Francisco, California, on February 11 in a paper about a 128-kbit SRAM that reads in 7ns and consumes 25-microwatts per megahertz

There is demand for reduced power consumption in microcontrollers aimed at mobile and wearable applications and these are often loaded with non-volatile memory such as embedded flash and ferroelectric RAM to store data. However, in operation SRAM is preferred because its speed of operation. As it becomes desirable to switch such microcontrollers on and off the ability for the SRAM to be available becomes a factor in power consumption.

Increasing leakage current is also a problem as device geometries shrink. Use of ferroelectric RAM (FRAM) as back-up eliminates the reload problem, but FRAM is slower in operation and consumes more active power than SRAM and adds to process complexity and cost.

The XLL SRAM presented by Toshiba reduces the leakage current by a factor of 1,000 compared with that of a conventional SRAM, Toshiba has claimed. This equates to a 27fA leakage current per bit when fabricated in a 65nm process. A 100-kbyte SRAM can retain data for over 10 years with a single battery charge, the company said.

Toshiba has achieved this by developing a transistor with a thick gate oxide, a long channel length and an optimized source-drain dopant diffusion profile. Other innovations include a circuit to apply back-bias to the NMOS transistor in the memory cell and another circuit to cut the supply voltage to peripheral circuits during data retention.

As a result the low-leakage transistor is larger than the conventional transistor in the same process but Toshiba said it has achieved a 20 percent reduction in the cell size by using alternative design rules

An SRAM with a 7ns read access is fast enough to be used with a low power MCU, the company claimed and said it plans to use the SRAM in a product released in 2014 for battery-based applications.

Related links and articles:

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