Semiconductors and Components

Startup Claims SRAM Halves Power Consumption

11 November 2013

SureCore Ltd. (Sheffield, England), a startup semiconductor IP company, has taped out an SRAM test chip in STMicroelectronics' 28-nm fully depleted silicon-on-insulator (FDSOI) process.

SureCore, founded in 2011, is looking to develop a range of memory IP—SRAM initially—for bulk, FinFET and FDSOI processes and it claims its first test chip will validate a patented array control and sensing scheme, which more than halves current offerings in the same process.

Memory is a function that is particularly sensitive to statistical variation and this is something SureCore claims to have a handle on allowing it to push performance and reduce power consumption. Because on-chip memory regularly exceeds 50 percent of the transistors in leading-edge chips power savings in on-chip memory is beneficial in reducing overall power consumption.

SureCore's SRAM IP was designed using advanced statistical models. In post-layout simulations the memory showed 75 percent less power for read cycles and 50 percent for write cycles, the company said. In addition, the technology promises improved leakage performance saving between 20 and 40 percent depending on operating corner, the company claimed.

"Although it is implemented in an FDSOI process, the innovations developed by SureCore are not process specific and will map to both bulk CMOS and FinFET technologies. We are currently working closely with partners to implement this in 40-nm and 28-nm bulk CMOS," said Paul Wells, CEO of SureCore, in a statement.

Duncan Bremner, chief technology officer of SureCore, said the SRAM IP offered "world-beating power consumption for SRAM-dependent system-on-chip solutions."

SureCore is a spin-off from Glasgow University and is working with simulation firm Gold Standard Simulations Ltd. (GSS) of Glasgow. Professor Asen Asenov, CEO of GSS and James Watt Professor of electrical engineering at the University of Glasgow, has a seat on the board of directors of SureCore.

"The novel circuitry developed both improves variability tolerance and lowers power consumption – key metrics for next generation SRAM solutions," Asenov said.

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