Soitec will supply Taiwanese foundry Powerchip Semiconductor Manufacturing Corp. (PSMC) with 300 mm substrates featuring an integrated release layer that is transistor layer transfer (TLT) ready to support advanced 3D chip stacking at the wafer level under a new agreement between the companies.
The goal is to enable more powerful, compact and energy-efficient next-generation semiconductor designs in applications like:
- Smartphones
- Tablets
- AI devices
- Automated driving systems
Soitec said the substrate stack will allow for high-speed transfer of ultra-thin transistor layers onto different types of wafers. This is a key requirement in heterogeneous integration where diverse chip components are collected in a single package.
Stacking allows multiple transistor layers to be built vertically to support 3D transistor architectures including vertical field-effect transistors (FETs) with backside power delivery networks (PDNs).
