How to become an expert in DDR memory test webinar series

Join Teledyne LeCroy for this four-part webinar to learn about physical layer double data rate (DDR) memory testing, from basic fundamentals through JEDEC DDR PHY compliance test, practical tips and techniques to increase user DDR debug skills and DDR validation efficiency, and the latest changes required for DDR5 memory test, including DDR eye diagrams and jitter measurements. Each webinar will run about 60 minutes and include a live Q&A. Source: Teledyne LeCroy

Register for this four-part webinar.

Part 1: Fundamentals of DDR memory testing

Presenter: Sriram Venkatesha, product manager
Date: Wednesday, September 25, 2024
Time: 11:00 AM Pacific | 2:00 PM Eastern

This webinar will offer a comprehensive introduction to DDR interfaces along with the challenges encountered during testing. The focus will be on distinguishing between validation and compliance testing requirements, as well as preparing for DDR memory testing.

Part 2: Tips and techniques for DDR probing

Presenter: Mike Hertz, senior field applications engineer
Date: Wednesday, October 9, 2024
Time: 11:00 AM Pacific | 2:00 PM Eastern

This webinar gets specific on how to address real-world probing and connectivity issues that impact DDR measurement capabilities. Examples will be provided of what to do or not do and a pre-compliance test checklist will be reviewed.

Part 3: DDR debug and virtual probing

Presenter: Mike Hertz, senior field applications engineer
Date: October 30, 2024
Time: 11:00 AM Pacific | 2:00 PM Eastern

This webinar provides practical advice on overcoming DDR test challenges using debug tools. Topics include real-world DDR debugging examples like logic, soldering and power supply issues, DDR read/write separation, eye pattern formation and addressing missing clock cycles. DDR eye patterns, jitter in multiple scenarios, hardware-based read-write separation, and virtual probing techniques will also be discussed.

Part 4: What’s new with DDR5 memory testing

Presenter: Sriram Venkatesha, product manager
Date: Wednesday, November 20, 2024
Time: 11:00 AM Pacific | 2:00 PM Eastern

This webinar will provide details on how the JEDEC DDR5 and LPDDR5 specification and test requirements are different from previous versions of DDR, and how users can optimize DDR5 and LPDDR5 memory testing.