As the common motherboard interface for PC cards graphics cards, solid-state drives, Ethernet hardware connections and more, Peripheral Component Interconnect Express (PCIe) is a versatile interface standard. Its high-speed data transfer capabilities, scalability and adaptability account for its adoption across a wide range of electronics industry segments, spanning from everyday consumer electronics to specialized applications in high-performance computing and critical infrastructure systems.
System Designer for PCIe is an intelligent design environment for modeling and simulating the latest PCIe Gen5 and Gen6 systems. Source: Keysight TechnologiesFor complex PCIe designs supporting multilink and multilane systems, however, designers often spend an inordinate amount of time preparing simulations that are prone to mistakes. Those simulations often lack vendor-specific algorithmic modeling interface (AMI) simulation models that would support design space exploration early in the design cycle. Designers also need assurance that their prototype design will pass compliance testing before hardware fabrication.
It's challenges like these that Keysight Technologies had in mind for the introduction of a new tool in its advanced design system (ADS) product suite. System Designer for PCIe is an intelligent design environment for modeling and simulating the latest PCIe Gen5 and Gen6 systems.
Keysight said the System Designer for PCIe simplifies the setup for multilink, multilane and multilevel PCIe systems through automation, reducing time-to-first-insight. With support for both NRZ and PAM4 modulations, the PCIe AMI modeler facilitates the quick AMI model generation needed for PCIe system analysis. Designers get a wizard-driven workflow for rapidly creating models for both transmitters (Tx) and receivers (Rx). A streamlined, simulation-driven PCIe compliance test workflow also enables designers to ensure design quality while reducing design costs by minimizing design iterations and shortening time-to-market.
Keysight also reports that it is adding new features to its Chiplet PHY Designer tool to estimate chiplet die-to-die link margin performance and Voltage Transfer Function (VTF) compliance measurement. The company says the tool is the electronic design automation (EDA) industry’s first simulation solution for Universal Chiplet Interconnect Express (UCIe) standards, enabling predictions of die-to-die link margin, VTF for channel compliance analysis and forwarded clock capability. The tool also includes new design exploration and report generation features designed to accelerate signal integrity analysis and compliance verification, improving designer productivity and time-to-market.
Keysight has produced a Standards Drive EDA Workflows webinar offering more information on these new tools in its ADS arsenal.
