Industrial Electronics

Video: Tektronix announces breakthrough Margin Test solution

12 December 2022

A new product category from Tektronix Inc. revolutionizes peripheral component interconnect express (PCIe) testing, transforming time to market, cost and accessibility. The new TMT4 Margin Tester breaks conventions of PCIe testing, delivering fast test times with plug-and-play set up and easy-to-use interface that combine to deliver in minutes results that, up until now, required hours or even days of set up and testing, often stretching costs to seven figures.

The TMT4 Margin Tester breaks new ground as a specialized testing tool for design and validation of PCIe Gen 3 and Gen 4 motherboards, add-in cards and system designs. While PCIe testing normally requires complex test systems and engineers with deep expertise and knowledge, the TMT4 Margin Tester enables engineers at all levels of experience to evaluate the health of transmitter (Tx) and receiver (Rx) links fasterSource: Tektronix Inc.Source: Tektronix Inc. than ever, greatly reducing time to market and cost of ownership. The platform supports the majority of common PCIe form factors, including CEM, M.2, U.2, and U.3, with testing capabilities of up to 16 lanes across PCIe presets 0-9, using a single standard connector.

The TMT4 tester is intended to complement full validation and compliance testing systems consisting of oscilloscopes and bit error rate testers, by making it possible to uncover issues earlier in the design process prior to an in-depth examination using traditional equipment. PCIe devices can be tested across 160 combinations of lanes and presets in as little as 20 minutes at Gen 4 speeds. Multi-lane testing capabilities enable users to significantly improve overall testing times by reducing the number of connection changes needed to perform testing.

Category-defining features

  • Quick Scan mode enables evaluation of link health for Gen 3 or Gen 4 devices, up to 16 lanes, in minutes, not hours or days.
  • Custom Scan mode provides deeper insights by enabling users to scan Gen 3 or 4 devices, up to 16 lanes, across PCIe presets 0-9 (up to 160 combinations) in as little as 20 minutes.
  • Simple setup and configuration minimize the need for senior-level engineers to perform link health evaluations of their designs.
  • Full Tx/Rx protocol capability that enables link health evaluation of PCIe Gen 3 and Gen 4 communication technologies on both sides of the link in a single box.
  • Multi-lane testing capabilities enable users to significantly improve overall testing times by reducing the number of connection changes needed to perform testing.
  • Visibility of link training parameters provides additional insights into which equalization was used to form the link.
  • Variety of adapters supporting the most common PCIe form factors for easy connection to motherboard and add-in card DUTs including CEM, M.2, U.2 and U.3.
To contact the author of this article, email engineering360editors@globalspec.com


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