Electronic design automation (EDA) trade organization Accellera Systems Initiative has published the latest IEEE 1666-2023 standard for SystemC language reference manual (LRM) as part of the IEEE GET program.
The standard addresses EDA and intellectual property’s need for a system design and verification language that spans hardware and software. The language is built in standard C++ by extending the language with use of class libraries.
"Our close partnership with the IEEE Standards Association is a tremendous benefit to design and verification engineers around the globe,” stated Lu Dai, chair of Accellera. “SystemC has been in use for more than two decades, and as the standard is revised Accellera will continue to leverage its relationship to provide SystemC and other much-needed standards to the community fee-free.”
The language is used for digital twins in the semiconductor space for embedded software development and hardware/software codesign. Additionally, SystemC is suited to model:
- Partitioning of systems
- Evaluate and verify the assignment of blocks
- Architect and measure interactions of functional blocks
Currently uses for SystemC in the EDA, IP, semiconductor, electronic systems and embedded software sectors include hardware/software co-design and virtual platforms, architectural exploration and deliver high-performance hardware blocks at various levels of abstraction.
What’s in the revision
The revision builds on enhancements and features contributed by the SystemC community for the past decade. The revision provides a new C++ baseline for using mature ISO C++ version and key capabilities like communicating with other simulations such as simulation stage callbacks or the suspend mechanism.
In all more than 50 topics in more than 10 categories were considered by the working group.
More information about the new standard update will be given at the SystemC Evolution Day held on Nov. 16, 2023, in Munich, Germany.
