Intellectual property (IP) house Arteris IP has signed an agreement with EDA tool supplier Magillem to accelerate system-on-chip architecture with multiple cores in a single environment.
The first part of the partnership is the validation of full compliance of Arteris IP interconnects with the Magillem environment. Using Magillem’s front-end design, users can import Arteris FlexNoc non-coherent interconnects and Ncore cache coherent interconnects using the IP-XACT format. This can then be used for full SoC assembly at the RTL and SystemC levels.
The companies said this integration eases the design of artificial intelligence (AI) and autonomous driving SoCs, which are now bonded by the performance of on-chip interconnects rather than performance of on-chip processors and hardware accelerators. The integration of the IP and tools enable automatic checking and synchronization of system memory maps and speeds up the creation of derivative chip designs.
Use of machine-readable IEEE IP-XACT data allows for automated traceability throughout the development flow, an important factor for compliance with functional safety standards such as the IEC 61508 and ISO 26262 for automotive systems.