A group of companies is working to test a new type of semiconductor, called cache coherent interconnect for accelerators (CCIX), that aims to be a starting point for enabling multi-core high-performance ARM-based CPUs working via a coherent fabric to off-chip field programmable gate arrays (FPGAs).
Xilinx, ARM, Cadence Design Systems and Taiwan Semiconductor Manufacturing Corp. (TSMC) are collaborating on the test CCIX chip for delivery scheduled in 2018 using TSMC’s 7 nm FinFET process technology.
Because applications in the data center are requiring more power and space, big data, machine learning, search, wireless 4G/5G, in-memory database processing, video analytics and network processing benefit from acceleration engines that move data seamlessly among system components.
CCIX will allow components to access and process data regardless of where it resides without any complex programming environments. The chip leverages server interconnect infrastructure and delivers higher bandwidth, lower latency and cache coherent access to shared memory. The companies say this results in significant improvement in the usability of accelerators and overall performance and efficiency of data center platforms
“With the surge in artificial intelligence and big data, we’re seeing increasing demand for more heterogeneous compute across more applications,” said Noel Hurley, VP and GM of the Infrastructure Group at ARM. “The test chip will not only demonstrate how the latest ARM technology with coherent multichip accelerators can scale across the data center but reinforces our commitment to solving the challenge of accessing data quickly and easily. This innovative and collaborative approach to coherent memory is a significant step forward in delivering high-performance, efficient data center platforms.”
The test chip will utilize TSMC 7 nm process and will be based on ARM’s DynamIQ technology, CMN-600 coherent on-chip bus and foundation IP. Cadence will provide key I/O and memory subsystems, including the CCIX IP solution (controller and PHY), PCI Express 4.0/3.0, DDR4 PHY and peripheral IPS such as I2C, SPI and QSPI. Cadence will also be supplying verification and implementation tools for the test chip. Xilinx’s 16 nm Virtex UltraScale+ FPGA will connect to the CCIX chip-to-chip coherent interconnect protocol.
