IBM and Korean electronics giant Samsung Electronics have developed a new semiconductor design for vertical transistors that potentially could reduce energy use by as much as 85% compared to fin field-effect (finFET) transistors.
The investment comes as the semiconductor market is impacted by an ongoing chip shortage. Research and development into new technologies is needed as the role of semiconductors is only growing in computing, appliances, communication devices, transportation systems and critical infrastructure, the companies said.
The vertical transistor architecture could help the chip industry by:
- Potentially enabling semiconductor device scaling to continue beyond nanosheet.
- Reducing recharge times with smartphone batteries potentially going over a week without needing a recharge.
- Requiring significantly less energy with a smaller carbon footprint for energy intensive processes like cryptofarming and data encryption.
- Expanding the internet of things and edge devices with lower energy needs, allowing these devices to operate in ocean buoys, self-driving cars and even spacecraft.
"Today's technology announcement is about challenging convention and rethinking how we continue to advance society and deliver new innovations that improve life, business and reduce our environmental impact," said Mukesh Khare, vice president of hybrid cloud and systems at IBM Research. "Given the constraints the industry is currently facing along multiple fronts, IBM and Samsung are demonstrating our commitment to joint innovation in semiconductor design and a shared pursuit of what we call 'hard tech.'"
How is it different?
According to Moore’s Law, the number of transistors in an IC chip will double every two years. This is quickly becoming impossible as the more transistor crammed into one area is finite.
Transistors have historically been built to lie flat on the surface of semiconductors with electric current flowing laterally. Instead, the vertical transport field effect transistors (VTFET) are built perpendicular to the surface of the chip with a vertical current flow.
The VTFET process extends Moore’s Law as designers are able to pack more transistors into a fixed space. Additionally, it allows for less wasted energy. The companies said the design could deliver a two times improvement in performance or 85% reduction in energy use compared to finFET.
IBM recently announced a 2 nm chip development, allowing it to fit up to 50 billion transistors in a space the size of a fingernail. VTFET would be a way to continue to pack more transistors onto future chips.