Industrial Electronics

New approach for next-gen memories with RRAM energy storage breakthrough

02 December 2021

In a breakthrough that is expected to significantly advance in-memory energy-storage in resistive-random access memory (RRAM) devices, CEA-Leti has proposed a “newfangled approach” that allows these devices to operate as energy-storage elements as well as memory, depending on the applied bias.

In-memory energy is a supplemental feature to in-memory computing, which is a key focus in CEA-Leti’s roadmap. It can reduce energy use dramatically because RRAM-based batteries are highly scalable and dynamically allocable, and they can be placed next to memory blocks, which are near the processor. Locating the energy supply close to the processor is especially helpful when the processor requires peak power, which typically comes from an external source.
This reduces power use over transmission lines while improving power-delivery network (PDN) efficiency. In The approach enables dual-behavior devices that can store data and energy. Source: CEA-LetiThe approach enables dual-behavior devices that can store data and energy. Source: CEA-Letiaddition to showing increased energy-and-power density, the hybrid, dual-behavior device proposed by CEA-Leti also is compatible with complementary metal-oxide-semiconductor (CMOS) fabrication processes.
“Our work attempts to tackle the modern demand of energy-efficient computation with an innovative approach, radically different from state-of-the-art solutions” said Gaël Pillonet, a senior expert at CEA-Leti. “This capability would be highly beneficial, allowing localized and high-bandwidth energy supply to the nearby processing unit and the memory. Our study is the first report on the feasibility of a practical implementation of the nanobattery effect in RRAMs, with quantification of the energy-and-power density capabilities, and a comparison with the best current solutions.”
RRAM is considered a leading candidate in next-generation memory because of its promising performance in scalability, in cost and CMOS-process compatibility.
The research results were reported in a recent paper in Advanced Electronic Materials, “In Memory Energy Application for Resistive Random-Access Memory.”
The high energy-and-power densities are due to the fact that the RRAM devices in the study rely on faradaic processes to store information inside an active volume, enabling the extracted values (power-and-energy densities) to far exceed that of electrostatic capacitors, and which are comparable to micro-supercapacitors. In addition, the technology is far more scalable: a cell size exhibits an area as low as 10-7 mm2, without loss of energy-storage capability, whereas state-of-the-art supercapacitors are around 10-3 mm2. That means the proposed devices are 104 times more scalable than the smallest-footprint micro-supercapacitors.
The high energy scalability is allowed by the small physical scale of RRAM devices, which involve a sub-nanometer-thick partial filament to store the energy: typical device areas are in the range of [0.1-1]10-7 mm2 and are expected to scale down in the near future.
Projected applications for these energy-use-cutting, dual-behavior devices include energy-to-memory (NAND and NOR Flash), energy-to-logic (internet of things processors) and neuromorphic uses (synaptic technology).
“Our study points out that energy storage in RRAM exhibits ‘local’ traits, similar to the memory effect, and thus does not increase with the device area, as opposed to standard solid-state batteries and micro-supercapacitors,” said Paola Trotti, a Ph.D. researcher and an author of the paper. “It follows that decreasing the size of samples, and connecting them in parallel, should allow for higher energy density. In addition, CMOS-compatibility supports downscaling, which increases with more advanced technology nodes.”
The research is a first step. Future work will aim to quantify the output voltage, columbic efficiency, experimental-energy and power-density capability in discharge mode, as well as proper peripheral circuits to deal with the memory/energy storage dual operation. More immediately, new design solutions in which the memory and energy performances are optimized will be explored to bring the technology to the application level.

To contact the author of this article, email engineering360editors@globalspec.com


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