Three RISC-V SoCs from Efinix

02 June 2020

Programmable product platform developer Efinix has announced the availability of a series of three software-defined, systems on a chip (SoCs) based on the popular RISC (reduced instruction set computer)-V® core.

The three designs have been optimized for Efinix’s Trion® family of field-programmable gate arrays (FPGAs) and provide a range of compute and I/O capabilities in devices from the T8 to the T120.

“RISC-V is a versatile and efficient embedded compute solution,” said Mark Oliver, senior director of marketing at Efinix. “Based on Charles Papon’s powerful and efficient VexRiscv design, our Trion® family of SoCs delivers pre-optimized RISC-V cores across the entire Trion FPGA product line from the cost-optimized T8 right up to the T120. Users can now easily create and deploy entire SoCs including embedded compute, I/O and custom functionality.”

For ease of use, the SoCs are preconfigured with a RISC-V core, memory, a range of I/O and have interfaces for embedding user functions. In this way, designers can easily create entire systems that include embedded compute and user-defined accelerators within the same FPGA.

“Since winning the RISC-V Soft CPU contest in 2018 and the Linux support addition, the VexRiscv core has been rising in popularity inside the open source community,” said Charles Papon, the designer of VexRiscv. “Optimizing the core into pre-defined configurations on the Trion family of FPGAs will give a much larger number of designers a turnkey and cost-effective way to access the power of the core in a broad variety of system designs.”

To contact the author of this article, email engineering360editors@globalspec.com


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