ArterisIP (Campbell, Calif.), a supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, 
has launched the Ncore Cache Coherent Interconnect IP version 3 along with the optional Ncore Resilience Package for functional safety.
Ncore 3 is a distributed heterogeneous cache coherent on-chip interconnect that enables SoC design teams to integrate processor clusters using the latest Arm® AMBA® CHI protocol (CHI Issue B). Key benefits include:
- Uniquely, Ncore 3 allows both AMBA CHI and ACE processor clusters and accelerators to operate as fully coherent peers in the same chip, giving design teams flexibility in choosing CPU and hardware accelerator IP. The ArterisIP CHI interface includes support for high level coherency semantics such as Atomics and Cache Stashing used by high-performance SoCs.
- The Ncore Cache Coherent Interconnect for Accelerators (CCIX) controller enables easy scaling of coherent systems across multiple chips via the Synopsys® DesignWare® Controller and PHY IP for PCI Express and CCIX.
- To enable advanced systems targeted at the automotive market, the Ncore 3 product line also includes the optional Ncore Resilience Package. This package accelerates customers’ ISO 26262 certification by offering: ISO 26262-compliant in-hardware functional safety mechanisms and a complete set of functional safety analyses and documentation.
The Ncore 3 Cache Coherent Interconnect IP is ideally suited for “supercomputer-on-a-chip” applications, such as those required for autonomous driving controllers and advanced driving assistance systems (ADAS), machine learning applications, server/data center processing and networking. Ncore’s highly configurable, distributed architecture allows design teams to more easily create complex systems that are more optimized for stringent power consumption, performance and area requirements.
“Development of Ncore 3 was driven by our customers’ desires to create large-scale high-performance computing and machine learning systems that conform to an embedded system’s power consumption and area requirements,” said K. Charles Janac, president and CEO of Arteris. “Ncore 3.0 interconnect IP builds on our proven Ncore cache coherent interconnect technology to implement functional safety features with Arm AMBA CHI protocol processors, permitting the entire SoC to be more easily qualified for ISO 26262 ASIL D for use in autonomous driving systems.”
The Ncore 3 Cache Coherent Interconenct IP and Ncore Resilience Package are available for early access customers in November 2017.
