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Semiconductors and Components

TSMC Adding Near-threshold Voltage Operation at 16nm

15 May 2015

Leading pure-play foundry Taiwan Semiconductor Manufacturing Co. Ltd (TSMC), headquartered in Hsinchu, has extended its 'ULP' family of processes with the announcement of an additional process at 16nm.

The move appears to be partly motivated by an intention to head off any possible competition from fully depleted silicon-on-insulator (FDSOI) processes developed by STMicroelectronics NV and offered by the foundry operation of Samsung Electronics.

The ability of the 16FFC process—for 16nm FinFET Compact—to outperform the 28nm FDSOI process currently being offered was discussed by Mark Liu, co-CEO of TSMC, in a mid-April conference call organized to discuss the company’s first quarter 2015 financial results.

The ULP family—for ultra-low power—are processes, introduced at the 55nm, 45nm and 28nm nodes that are specified for operating voltages that can be reduced by 20% to 30% from previous norms at each node. By offering the ability to scale voltage downwards, TSMC is allowing users to reduce power consumption, which scales with the square of voltage, and extend battery life of equipment by a factor of between two and 10, the company claims.

Thus, the ULP variant of manufacturing process has been aimed at ICs for wearable equipment and for the Internet of Things (IoT). Now, TSMC has said it will introduce a 16FFC variant of its 16FF+ process.

The process operates at a nominal voltage of 0.55V and can cut power consumption by 50% compared with 16FF+, TSMC has reportedly said. Design support is due to be available in the first quarter of 2016 with product tape-outs due in the second half of next year.

In the recent financial analysts' conference April 16, Liu said the ULP family overall has 30 product tape-outs planned for 2015. None of them are for the 16nm version and are likely to include CSR, Fujitsu Semiconductor, Nordic Semiconductor, Realtek and Silicon Labs—five companies mentioned as early customers for the ULP family (see TSMC Tips Low-Voltage Processes Aimed at Wearables, IoT).

"This 55- and 40-nanometer ULP will be the most cost-effective solution for low-to-mid performance wearable and IoT devices. The 28 ULP and 16 FFC will be the most power-efficient solutions for high performance IoT applications," says Liu. "In particular, our 16FFC offers the ultra-low power operation at a supply voltage of 0.55 volts with higher performance of all of the FDSOI technologies marketed today."

"What's really happening is that TSMC, Samsung and to a degree Intel are competing for the very lucrative next major potential volume application," says Len Jelinek, senior director of semiconductor manufacturing IHS Technology.

Len Jelinek, senior director of semiconductor manufacturing IHS Technology Len Jelinek, senior director of semiconductor manufacturing IHS Technology The leading foundries also appear to be trying to get ahead of each other in terms of basic technology platforms at the advanced nodes, then offer multiple varieties of that platform at a later date. "If the company were to actually take the time to complete the full technology shelf, then the potential big customer may not wait," Jelinek says.

"The 14/16nm node is not a pure 14nm or 16nm set of design rules. It is really a 20nm back end. Samsung and TSMC are trying to go fast to get business and Qualcomm and Apple are showing no loyalty," Jelinek adds. "It's all about being in the right spot to gain the business before the competition can do so."

Questions or comments on this story? Contact: peter.clarke@ihs.com

Related links and article:

www.tsmc.com

IHS Semiconductor Manufacturing Research

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