A consortium comprised of electronics companies – including chip designers and OEMs – has released its first global standard to enable the design of hybrid memory cube technology (HMC).
The final specification marks the turning point for designers in a wide range of segments – including the networking, high-performance computing and industrial sectors – to begin designing Hybrid Memory Cube (HMC) technology into future products, the HMC Consortium (HMCC) announced this week.
A major breakthrough with HMC is the long-awaited utilization of advanced technologies to combine high performance logic with state-of-the-art DRAM, the group said. With this first HMC milestone reached in 17 months, consortium members have elected to extend their collaborative effort to achieve agreement on the next generation of HMC interface standards.
Members of the consortium include Altera, ARM, HP, IBM, Micron Technology, Open-Silicon, Samsung Electronics, SK Hynix and Xilinx.
As envisioned, HMC architectures will offer improvements in performance, packaging and power efficiency over current memory architectures.
One of the primary challenges facing the industry – and a key motivation for forming the HMCC – is that the memory bandwidth required by high-performance computers and next-generation networking equipment has increased beyond what conventional memory architectures can efficiently provide, the consortium said. The term “memory wall” has been used to describe this challenge. Breaking through the memory wall requires an architecture such as HMC that can provide increased density and bandwidth with significantly lower power consumption.
The HMC standard focuses on alleviating an extremely challenging bandwidth bottleneck while optimizing the performance between processor and memory to drive high-bandwidth memory products scaled for a wide range of applications. The need for more efficient, high-bandwidth memory solutions has become particularly important for servers, high-performance computing, networking, cloud computing and consumer electronics.
The next goal for the consortium is to further advance standards designed to increase data rate speeds from 10, 12.5 and 15 gigabits per second (Gb/s) up to 28 Gb/s for short reaches and from 10 Gb/s up to 15 Gb/s for ultra-short reaches. The next-generation specification is projected to gain consortium agreement by the first quarter of 2014.
