Applied Material’s Reflexion LK Prime CMP system is an enabler for FinFET gate and the staircase structure in 3-D NAND memory. The tool was created to address the exacting requirements of 3-D device architectures that can require as many as 10 additional polishing steps. The tool features six polishing stations and eight integrated cleaning stations with process control technologies and supports the added CMP steps to improve on-wafer performance and throughput.
As a result, Applied said the increase in processing modules doubles wafer throughput for many applications, providing up to a 100 percent boost in productivity.
According to Applied, having the ability to independently utilize each polish and cleaning station gives chipmakers new levels of flexibility to customize polishing passes to precisely control feature dimensions and reduce defects. Other features of LK Prime system include real-time profile and endpoint control technologies allowing for FinFET gate controls with nanometer-level uniformity for every die, a needed control feature for the long, steady polishes required of 3-D NAND design.
"Trends in mobility are driving the need for complex 3-D architectures that demand significant engineering innovations," said Dr. Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials, in a statement. "An entire spectrum of new technologies and materials are needed for these designs to achieve optimum device performance and high yields. Multiple customers are adopting the tools we are launching today, demonstrating the value of our latest technologies in transitioning their advanced 3-D logic and memory designs into volume manufacturing."
3-D NAND manufacturing requires enabling deposition technology for vertical gate formation and patterning applications. The Producer XP precision CVD tool supports the 3-D NAND transition by delivering nanometer-level layer-to-layer fil thickness control for CD uniformity across the wafer. The tool allows the ability to tune crucial parameters that include temperature, plasma and gas flow. This flexibility supports the alternate deposition of different high-quality, low-defect films with stress control and uniformity within-wafer, wafer-to-wafer and layer-to-layer to improve gate performance and reduce device variability, Applied said.
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