The China Times reported in April that Apple is using system-in-package (SiP) technology to implement the Wi-Fi and fingerprint-recognition modules in its nascent iWatch. Couple this news with recent predictions that the SiP market will undergo rapid expansion and it becomes apparent that the technology is poised to assume a greater role in electronics design. But why now? After all, SiP is no newcomer to the electronics industry. Wireless and consumer-focused electronics providers have been refining the packaging technology since its debut in the late 1990s. Some might point to advances in design, modeling, and interconnection technologies as reasons, and they would be partially right. The truth is the emergence of the Internet of Things (IoT) and the new demands it makes on electronic devices is the underlying force driving SiP’s ascent.
“The IoT is about developing highly integrated, small form factor devices, or nodes,” says Gil Reiter, Strategic Manager for IoT at Texas Instruments. “The first challenge is integration – making the devices as small as possible, with higher levels of functionality. The second challenge is to produce low-power technologies to support the growing number of battery-operated devices. And the third is to enable cost-effective, high-volume production, because the IoT will encompass so many devices.”
SiP, however, is not the only technology enabling this transformation. It joins system-on-a-chip (SoC), among others, in the quest to enable greater functionality in smaller form factors. Both technologies seek to integrate several technologies and complementary functions to achieve tangible gains in space reduction and optimal system-level performance at the lowest price point.
“These are complementary technologies,” says William Chen, Senior Technical Advisor at Advanced Semiconductor Engineering (ASE). “It is not a question of using one or the other. The industry uses both tools to make products work better for the end user.”
Two Approaches to Integration
While SoC and SiP complement one another, they are not interchangeable. Each takes a different approach to miniaturization and delivers unique advantages.
An SoC integrates circuitry and functions such as microprocessors, memory, signal processing, and output logic, on a single piece of silicon, instead of assembling several chips and components onto a circuit board. The SoC offers small system size and good performance that can be mass-produced at low cost.
Texas Instrument’s CC2530 SoC integrates 256 KB of flash memory, a ZigBee RF transceiver, and a microprocessor on a single piece of silicon. (Photo courtesy of Texas Instruments.)
In an SiP, ICs performing different functions are stacked in a single package. Like SoC, SiP combines various functions and memory, but it can more easily go one step further. Because all components are not fabricated on the same die, SiP can combine building blocks built on fundamentally dissimilar silicon technologies, sidestepping hurdles that often prevent SoC from including components like MEMS sensors. This feature also opens the way for designers to use best-in-class components to optimize their system’s performance.
Adding MEMS to the Mix
High on the list of IoT-enabling technologies, sensors provide a link to the physical world. Whether they are building a smart light bulb or an intelligent refrigerator, the makers of IoT devices tap the full range of sensing technology, from temperature and pressure sensors to accelerometers and gyroscopes. Because of the size and energy efficiency requirements demanded by these applications, designers often see MEMS devices as the optimal choice.
Of the two design approaches, SiP presents the fewest obstacles to incorporation of MEMS devices. With the SoC, the impediments are significant. The capacity to practically incorporate MEMS technology is a key differentiator between the two technologies.
SiP enables greater functional density, using the package to combine multiple ICs — such as MEMS sensors, radios, and microprocessors — in a single module. (Photo courtesy of Zuken.)
The obstacle complicating the inclusion of a MEMS device on an SoC is the fact that the two structures are produced by fundamentally different processes. “While sensor fusion technology can combine CMOS and MEMS on the same die, the process compromises the effectiveness of both sensor and processor,” says Glenn Daves, Director of Packaging Solutions Development at Freescale Semiconductor.
This leaves the designer with two choices. Either have the MEMS and the SoC as separate chips and take up more space, or turn to SiP technology.
“The fact that it is such a challenge from a manufacturing perspective to put sensors on the same SoC as the microcontroller implies that you are going to have a two-chip solution,” says Joel Rosenberg, platform marketing director at ARM.”
Problems with Wireless
The other major building block being added to systems to meet the demands of the IoT is the radio. As with MEMS sensors, the inclusion of this functionality can be challenging. Some electronics providers add wireless connectivity to the system using a discrete radio on a separate die. Others build the radio capabilities onto the same chip as the processor. Both approaches add complexity to the design process and can degrade system performance.
Problems arise when the radio is deployed near the microprocessor and memory. Radio-frequency interference can degrade or limit the performance of the system. “If you have an SiP, you have to do localized RF noise mitigation,” says ARM’s Rosenberg. “But if you are building an SoC, and you have the radio on the same chip as the processor and logic, then you have to worry not only about the noise relative to the radio circuitry but also the impact of the radio on the other parts of the circuit on the SoC.”
Dealing with Complexity
While the complexities of SoC and SiP differ in nature, both have a significant impact on the design process. Failure to deal with these issues through modeling and simulation can seriously compromise performance.
To create an SoC, each functional block must be designed separately or selected from the vendor's IP blocks. Then to ensure that the blocks function properly, the design team uses circuit simulation for individual devices and logic blocks, characterizing their functional behavior. For the actual chip design, the designers use a high-level language like VHDL or Verilog.
“The SoC concept of integrating everything on monolithic silicon is a great idea,” says Gene Matter, Vice President of Application Engineering at DOCEA Power. “But as I discovered when I worked at Intel, fabricating memory technology, high-performance logic, and analog all in the same process is expensive. In addition, some elements like analog circuits don’t scale nicely with process technology.”
SiP has its own drawbacks. The technology’s architecture is determined by the collection of individual dice that go into the package. This may include a radio, MEMS sensors, and a microcontroller, all on separate dice, connected by a substrate. The design process becomes complex at this point because the designers must arrange the dice so that they can all be interconnected on the same plane. The interconnections pass through the dice themselves, so the design team must anticipate how the dice are going to be attached.
Thermal management is also an issue that must be evaluated in relation to placement and orientation of the dice. Roughly, 96% of the heat. regardless of the source, dissipates through the dice. As a result, die interconnects are an important design consideration. Because most of the heat is transferred from the sources to the dice, transfer distances play a large part in determining the temperature gradient and the package thickness.
Docea Power’s AceThermalModeler can be used to simulate coupling between power and temperature systems to enable designers to detect potential thermal issues early in the project design flow. (Screen courtesy of Docea Power.)
“It gets even more complicated when you begin to include analog circuits, like RF or power amplifiers, which have their own response to heat levels,” says Matter.
In addition to the thermal issues, SiPs are more complicated electrically than SoCs. As the number of dice goes up, the current increases, and the dice become more susceptible to electromagnetic noise and timing affects.
“The electrical challenges include dealing with parasitics in silicon interflows or through silicon vias,” says Larry Williams, Director of Product Management at Ansys. For example, each through-silicon via (TSV) has the potential to couple electromagnetically with another. Parasitics coupling can cause the chip to run at a slower speed because the parasitics are slowing down the signaling and therefore the chip cannot operate at full capacity. So advanced physics and circuit simulation tools allow engineers to analyze those issues.”
Tipping the Scales
SoC and SiP both offer technological advantages, and the two approaches can be used together in the same system. Market considerations and the unique demands of the IoT, however, may make SiP more attractive to the designer in some applications.
Because an SiP can combine off-the-shelf components, its design cycles are often shorter and fabrication costs lower than an SoC. “To design and develop a new chip takes time and money,” says ASE’s Chen. “Sometimes instead of trying to develop new designs for the next node, a designer can reuse a previously designed chip in an SiP and cut the time to market. You have to balance business and technology considerations when choosing a methodology.”
In addition, the complex design process for an SoC may preclude smaller companies from adopting the approach. “The SoC is more complex than the SiP from a design methodology perspective because the design team must have a broader range of expertise to ensure this variety of components work well together on a single die,” say ARM’s Rosenberg. “You are calling on people with different skill sets to work together to build an integrated SoC. Few small companies and startups have this depth of expertise. So it’s easier to buy individual components off the shelf than to design a complex chip that has it all on the same die.”