Fabless chip company Kalray SA (Orsay, France) has demonstrated its 256-core processor being used as an HEVC encoder for a 4K-resolution video stream.
Kalray's demonstrator uses the MainConcept HEVC SDK that is capable of encoding a 4K HEVC video at 30fps using four 28nm MPPA-256 processors, which consume less than 50 watts altogether. The DivX HEVC video was due to be streamed to a 4K TV set at a Chinese Broadcasting Exhibition being held in Beijing, last week.
DivX LLC, a subsidiary of Rovi Corp. (Santa Clara, Calif.) provides end-to-end solutions for digital streaming and video streaming that includes adaptability in terms of the final screen and digital rights management.
MainConcept is an encoding SDK for professional content creators with DRM for protected content delivery across multi-screen devices. In addition, DivX HEVC is integrated into a certification program that allows IC and OEM customers to bring mobile and consumer electronics products that play DivX HEVC video.
Kalray was founded in 2008 and is led by Joel Monnier, a former vice president of central R&D at Europe's largest chip company STMicroelectronics NV. The company was well funded having raised $27 million in its first three years to pay for its initial chip design. The company started sampling its 256-core processor, implemented in 28nm CMOS in 2012.
The MPPA-256 implements a proprietary VLIW architecture and integrates an IEEE 754 floating-point unit. The 256 processors are organized as 16 clusters of 16 processors and communicate with each other via a network-on-chip. Multiple MPPA chips can be interconnected at the PCB level through Interlaken interfaces to increase the processor array size and performance capability as has been done in the HEVC encoder demo.
When Kalray first emerged from stealth mode in 2011 it was aiming its chip at a broad set of applications that can benefit inherently from parallelization, including: imaging, telecommunications infrastructure, data security and networking.
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