Semiconductor Equipment

Imec demos logic and DRAM on high NA EUV lithography

08 August 2024
Imec has demonstrated an integration of the storage node landing pad with a bit line periphery for DRAM. Source: Imec

Belgium research hub Imec has successfully demonstrated patterned structures obtained after exposure with the 0.55 high numerical aperture (high NA) extreme ultraviolet (EUV) scanner at the joint ASML-Imec lithography lab in Veldhoven, The Netherlands.

The ASML-Imec lab was established in June to provide logic, memory chip makers, materials and equipment suppliers access to the first prototype high NA EUV scanner as well as processing and metrology tools.

Imec patterned random logic structures down to 9.5 nm, random vias with 30 nm center-to-center distance, 2D features at 22 nm pitch and a DRAM specific layout at P32 nm printed after a single exposure. Imec said these patterns confirm the readiness of the ecosystem to allow single exposure high resolution high NA EUV lithography.

“The results confirm the long-predicted resolution capability of High NA EUV lithography, targeting sub 20nm pitch metal layers in one single exposure,” said Luc Van den hove, president and CEO of Imec. “High NA EUV will therefore be highly instrumental to continue the dimensional scaling of logic and memory technologies, one of the key pillars to push the roadmaps deep into the ‘angstrom era. These early demonstrations were only possible thanks to the set-up of the joint ASML-imec lab allowing our partners to accelerate the introduction of High NA lithography into manufacturing.”

Additionally, Imec successfully patterned a single exposure design that integrates the storage node landing pad with the bit line periphery for DRAM. This will allow High NA technology to replace the need for several mask layers with one single exposure, Imec said.

To contact the author of this article, email PBrown@globalspec.com


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