For technologies such as IoT devices, mobile phones and Ethernet interfaces, two parallel industry trends have made the need for design accuracy greater now than it’s ever been before. First, the ever-growing demand for greater capabilities, higher speeds and better efficiency have increased the complexity of system-on-chip (SoC) and application-specific integrated circuit (ASIC) designs. At the same time, customers are demanding access to new capabilities at an ever-increasing rate, translating to shorter time to market for chipset vendors.
The pain point comes when issues are found in silicon chips after fabrication, which can mean costly re-spins, software patching, more resources poured into quality assurance (QA) and negative brand image impacts — making it essential to identify and resolve defects early in the development cycle.
One of the more challenging aspects of this task is the creation of meaningful Ethernet traffic generation, along with testing and troubleshooting capabilities — traditionally the purview of post-silicon validation. Bridging that gap between pre- and post-silicon verification is the aim of a just-announced collaboration between two longtime partners: Spirent Communications and Cadence Design Systems.
According to a press release, the two companies have combined forces to produce a joint networking system-on-chip (SoC) verification solution with a high degree of both flexibility and scalability. Among the most impressive aspects of the solution is its capability to emulate any port speed from 1G to 800G at the application level and quickly introduce additional features to enable new use cases.
Behind the scenes is the integration of Spirent’s virtual Ethernet traffic emulation and test capabilities with Cadence’s flagship Palladium Z2 Enterprise Emulation platform and Protium X2 Enterprise Prototyping systems.
Additional solution benefits include:
- Comprehensive integration of the test application and emulation environment without the need for external test hardware.
- Continuity of testing from the earliest phases of product development through customer deployment
- Capability to test all phases of silicon product lifecycle
- Time-saving application re-utilization
- Implementation of standard metrics for measurement and result analysis
- Easy integration into continuous integration/continuous deployment (CI/CD) workflows
- Acceleration of the entire silicon development lifecycle
A short video with more detail about the solution is available on the Cadence website.