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Memory and Storage

Spin-orbit Torque MRAM Demonstrated on 300-mm Wafers for the First Time

18 June 2018

The performance of the SOT-MRAM. Source: ImecThe performance of the SOT-MRAM. Source: ImecResearch house Imec is demonstrating the potential of fabricating spin-orbit torque MRAM (SOT-MRAM) devices on 300-mm wafers using CMOS compatible processes for the first time during this week’s 2018 Symposia on VLSI Technology and Circuits.

SOT-MRAM devices manufactured on 300-mm wafers offer unlimited endurance, fast switching speeds and low power consumption and could one day replace L1/L2 SRAM cache memories in high performance computing applications.

Imec said SOT-MRAM has recently emerged as a non-volatile memory technology that can overcome the limitation of spin-transfer torque in MRAM memories. So far, however, it has only been demonstrated in a lab. Imec was able to fabricate SOT-MRAM device modules on 300-mm waters using CMOS-compatible processes.

The core of the SOT-MRAM is a magnetic tunnel junction in which a thin dielectric layer is sandwiched between a magnetic fixed layer and a magnetic free layer. SOT-MRAM devices feature switching of the free magnetic layer done by injecting an in-plane current in an adjacent SOT layer, unlike STT-MRAM where the current is injected perpendicularly into the magnetic tunnel junction and the read and write operation is performed through the same path.

The switching behavior of the SOT device is similar to what is found on STT-MRAM but with unlimited endurance. In SOT-MRAM the magnetic tunnel junction consists of an SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetized stack, using beta-phase tungsten for the SOT layer.

Future steps of this technology will work to further reduce the energy consumption by bringing down current density and by demonstrating field-free switching operation.

To contact the author of this article, email Peter.Brown@ieeeglobalspec.com


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