Maxim Integrated Products Inc. (San Jose, Calif.) is working on its own design of 16bit RISC processor core in an asynchronous logic, or clockless, format for the sake of power saving.
The core is intended for use in low power microcontrollers will be a version of Maxim's MaxQ 16bit RISC core. The core will run clockless but will have clocked peripheral circuits and I/O, the company said. The R&D is being done in Dallas, Texas, under Dan Loomis, vice president responsible for medical, energy and embedded security business unit.
Excepting one or two instances asynchronous or clockless logic appears to have fallen out of favor in recent years with R&D efforts on extreme power saving turning instead to clocked logic run at near- or sub-threshold voltages.
However, Maxim has joined such companies as Wave Semiconductor Inc. (Sunnyvale, Calif.) and Tiempo SA (Grenoble, France). The original argument in favour of asynchronous logic was that it could save power compared with equivalent clocked circuits but problems with testing of asynchronous circuits performance variability against temperature seemed to weigh against usage.
Asynchronous logic and security
But now one of the reasons for the adoption of asynchronous logic could be that it can be used to achieve greater data security more power efficiently than conventional clocked logic.
Clocked logic can produce an instantaneous power consumption that is indicative of specific data being processed as part of key cryptography. Analysis of that power consumption profile can be used to extract keys unless developers have gone to the trouble of adding dummy circuitry to balance out the power consumption and prevent differential power analysis (DPA). That dummy circuitry adds to power consumption. By contrast, asynchronous logic does not produce large current draw spikes on a clock cycle but rather looks like a continuous "noisy" power consumption that does not reveal information about numbers (keys) being processed so readily.
When asked what sort of power saving Maxim is seeing in its asynchronous design Loomis told Electronics 360: "That’s very application specific. A big advantage is that supply voltage can be a lot lower. At the same Vcc, we expect 15 percent savings but that doesn't tell the full story since the equivalent processing is also possible at lower Vcc where the synchronous design will fail. For example, going from 1.8V to 0.8V will save 85 percent of the total energy for CPU and memories, measured in nJ."
To get round the issue of testing Maxim has design its MaxQ core to have both synchronous and asynchronous modes of operation. Testing is done synchronously both for the functionality as well as for the asynchronous delay elements to guarantee coverage, Loomis said. He added that a patent filing on this technique should be viewable online soon.
Loomis said the first implementation of the asynchronous MaxQ is designed for a 130-micron manufacturing process with embedded flash with the intention that an MCU design will be offered to customers in the first half of 2015. The chip will operate from a 3V supply with internal voltage regulation for the core of the chip. "The core voltage will be lower than for a comparable synchronous design but is not finalized yet," Loomis said.
Electronics 360 also asked Loomis if the development group has also looked at near-threshold operation, which would imply voltages somewhere around or below 0.6V. Loomis answered affirmatively but did not elaborate.
When asked why Maxim's Dallas-based R&D team was not applying the approach to an ARM Cortex-M3 core, Loomis said: "We don’t have an architectural license from ARM, which means we can’t monkey around with the core." He added that an architectural license is very expensive and very rare.
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