Electronics and Semiconductors

Rambus plans a day of technical sessions at DesignCon

26 January 2023

Rambus will host a day of technical sessions at DesignCon, the high-speed communications and system design conference and exposition scheduled for January 31 through February 2, 2023, at the Santa Clara, California, Convention Center.

Hear from experts on the technologies that are set to shape the future of data centers and high-performance systems, and discover how cutting-edge memory, interconnect and security IP solutions from Rambus enable today’s most challenging computing, edge, automotive and internet of things applications.

Register and learn more about DesignCon and schedule a meeting with Rambus representatives.

Source: RambusSource: Rambus

These sessions will be held on February 1 in Great America 1:

8:00 AM to 8:45 AM: Technologies that will shape the future of the data center — Server and data center architectures are rapidly evolving in response to the growing volume and importance of digital data. The meteoric rise of artificial intelligence/machine learning (AI/ML) and advanced workloads accelerate this change. New memory and interconnect technologies are key to tackling a growing list of challenges that architects must address to meet the needs for future data centers.

9:00 AM to 9:45 AM: Choosing the right high-performance memory solution — Demanding workloads such as AI/ML training, network graphics and HPC have led to the development of application-specific silicon. To keep these processors and accelerators fed requires state-of-the-art memory solutions that deliver extremely high bandwidth. Performance, design and implementation considerations need to be examined in selecting the right memory for next-generation computing applications.

11:15 AM to 12:00 PM: Automotive IP solutions for the software-defined vehicle — Automotive systems, and the semiconductors used within them, are some of the most complex electronics seen today. That complexity is set to dramatically rise as cars reach new levels of automation. This panel will explore some of the main technical and certification challenges facing automotive designers and discuss how IP solutions can help meet demanding performance, safety and security requirements.

12:15 PM to 1:00 PM: Memory encryption solutions for protecting data in use — There are many challenges to achieving good “memory security,” especially in that the term “memory” could refer to on-chip SRAM, embedded non-volatile memory (NVM) or even off-chip memory (both DRAM and mass-storage non-volatile). We refer to data within non-executable NVM to be “data at rest,” while data within volatile memory like SRAM or DRAM to be “data in use.” In both domains, data within these memories is of interest to an adversary — it has either immediate value (passwords, secret keys, AI/ML datasets, etc.), or it can indirectly lead to exposure of those valuable assets. This presentation will focus on the key aspects of memory security for data-in-use applications: 1) data privacy, 2) data authenticity and 3) data freshness, and how those security aspects weigh against critical performance metrics including latency and memory overhead.

2:00 PM to 2:45 PM: Accelerating data interconnects with PCI Express 6.0 Interface IP — The latest generation of PCI Express (PCIe) 6.0, advances performance to 64 GT/s in support of advanced data center workloads and networking. In this presentation, interface technology experts will discuss the new features implemented in PCIe 6.0, such as PAM4 signaling and low-latency forward error correction (FEC). They will also show how Rambus PCIe interface IP can support future design requirements.

3:00 PM to 3:45 PM: CXL advances data center performance with memory tiering architecture — CXL technology promises tremendous gains in computing performance by bridging the latency gap between direct-attached DRAM main memory and solid-state storage. Rambus CXL experts will discuss the market requirements and technology challenges addressed by memory tiering. Memory tiering solutions, and their many possible deployments, as well as software orchestration and management of tiered-memory architectures will be discussed.

To contact the author of this article, email GlobalSpecEditors@globalspec.com

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